CS 105

Tour of the Black Holes of Computing

The Memory Hierarchy

Topics
 Storage technologies and trends
 Locality of reference
 Caching in the memory hierarchy
Random-Access Memory (RAM)
Key features
 RAM is packaged as a chip
 Basic storage unit is a cell (one bit per cell)
 Multiple RAM chips form a memory
Static RAM (SRAM)
 Each cell stores bit with a six-transistor circuit
 Retains value indefinitely, as long as it is kept powered
 Relatively insensitive to disturbances such as electrical noise
 Faster and more expensive than DRAM
Dynamic RAM (DRAM)
 Each cell stores bit with a capacitor and transistor
 Value must be refreshed every 10-100 ms
 Sensitive to disturbances
 Slower and cheaper than SRAM
–2– CS 105
Non-Volatile RAM (NVRAM)
Key Feature: Keeps data when power lost
 Several types
 Most important is NAND flash
 Ongoing R&D
NAND flash
 Reading similar to DRAM (though somewhat slower)
 Writing packed with restrictions:
 Can’t change existing data
 Must erase in large blocks (e.g., 64K)
 Block dies after about 100K erases
 Writing slower than reading (mostly due to erase cost)
 Chips often packaged with Flash Translation Layer (FTL)
 Spreads out writes (“wear leveling”)
 Makes chip appear like disk drive

–3– CS 105
Conventional DRAM Organization
d x w DRAM:
 dw total bits organized as d supercells of size w bits

16 x 8 DRAM chip
cols
0 1 2 3
2 bits 0
/
addr
1
rows
memory supercell
2
controller (2,1)
(to CPU)
3
8 bits
/
data

–4– internal row buffer CS 105

Reading DRAM Supercell (2,1)
Step 1(a): Row address strobe (RAS) selects row 2
Step 1(b): Row 2 copied from DRAM array to row buffer
16 x 8 DRAM chip
cols
0 1 2 3
RAS = 2
2
/ 0
addr
1
rows
memory
controller 2

8 3
/
data

–5– internal row buffer CS 105

Reading DRAM Supercell (2,1)
Step 2(a): Column access strobe (CAS) selects column 1
Step 2(b): Supercell (2,1) copied from buffer to data lines,
and eventually back to CPU
16 x 8 DRAM chip
cols
0 1 2 3
CAS = 1
2
/ 0
To CPU addr
1
rows
memory
controller 2

supercell 3
8
(2,1) /
data

supercell
–6– internal row buffer CS 105
(2,1)
Memory Modules
addr (row = i, col = j)
: supercell (i,j)
DRAM 0
64 MB
memory module
consisting of
DRAM 7
eight 8Mx8 DRAMs

bits bits bits bits bits bits bits bits

56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7

63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Memory
controller
64-bit doubleword at main memory address A

64-bit doubleword
–7– CS 105
Typical Bus Structure
Connecting CPU and Memory
A bus is a collection of parallel wires that carry
address, data, and control signals
Buses are typically shared by multiple devices

CPU chip

register file

ALU

system bus memory bus

I/O main
bus interface
bridge memory

–9– CS 105
Memory Read Transaction (1)
CPU places address A on memory bus

register file Load operation: movl A, %eax

ALU
%eax

main memory
I/O bridge 0
A
bus interface x A

– 10 – CS 105
Memory Read Transaction (2)
Main memory reads A from memory bus, retrieves word
x, and places it on bus

register file
Load operation: movl A, %eax

ALU
%eax

main memory
I/O bridge x 0

bus interface x A

– 11 – CS 105
Memory Read Transaction (3)
CPU reads word x from bus and copies it into register
%eax

register file Load operation: movl A, %eax

ALU
%eax x

main memory
I/O bridge 0

bus interface x A

– 12 – CS 105
Memory Write Transaction (1)
CPU places address A on bus; main memory reads it
and waits for corresponding data word to arrive

register file Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0
A
bus interface A

– 13 – CS 105
Memory Write Transaction (2)
CPU places data word y on bus

register file Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0
y
bus interface A

– 14 – CS 105
Memory Write Transaction (3)
Main memory reads data word y from bus and stores it
at address A

register file
Store operation: movl %eax, A

ALU
%eax y

main memory
I/O bridge 0

bus interface y A

– 15 – CS 105
Disk Geometry
Disks consist of platters, each with two surfaces
Each surface consists of concentric rings called tracks
Each track consists of sectors separated by gaps
tracks
surface
track k gaps

spindle

sectors
– 16 – CS 105
Disk Geometry
(Muliple-Platter View)
Aligned tracks form a cylinder
cylinder k

surface 0
platter 0
surface 1
surface 2
platter 1
surface 3
surface 4
platter 2
surface 5

spindle

– 17 – CS 105
Disk Operation (Single-Platter
View)
The disk
Read/write head
surface
is attached to end
spins at a fixed
of the arm and flies over
rotational rate
disk surface on
thin cushion of air

spindle

By moving radially, arm can

position read/write head
over any track

– 20 – CS 105
Disk Operation (Multi-Platter
View)
read/write heads
move in unison
from cylinder to cylinder

arm

spindle

– 21 – CS 105
Disk Access Time
Average time to access some target sector approximated by :
 Taccess = Tavg seek + Tavg rotation + Tavg transfer
Seek time (Tavg seek)
 Time to position heads over cylinder containing target sector
 Typical Tavg seek = 9 ms
Rotational latency (Tavg rotation)
 Time waiting for first bit of target sector to pass under r/w head
 Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min
Transfer time (Tavg transfer)
 Time to read the bits in the target sector.
 Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min

– 22 – CS 105
Disk Access Time Example
Given:
 Rotational rate = 7,200 RPM
 Average seek time = 9 ms
 Avg # sectors/track = 400
Derived:
 Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms
 Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02
ms
 Taccess = 9 ms + 4 ms + 0.02 ms
Important points:
 Access time dominated by seek time and rotational latency
 First bit in a sector is the most expensive, the rest are free
 SRAM access time is about 4 ns/doubleword, DRAM about 60 ns
 Disk is about 40,000 times slower than SRAM, and
 2,500 times slower then DRAM
– 23 – CS 105
Logical Disk Blocks
Modern disks present a simpler abstract view of the
complex sector geometry:
 The set of available sectors is modeled as a sequence of b-
sized logical blocks (0, 1, 2, ...)
Mapping between logical blocks and actual (physical)
sectors
 Maintained by hardware/firmware device called disk
controller
 Converts requests for logical blocks into
(surface,track,sector) triples
Allows controller to set aside spare cylinders for each
zone
 Accounts for the difference in “formatted capacity” and
“maximum capacity”

– 24 – CS 105
I/O Bus
CPU chip
register file

ALU
system bus memory bus

I/O main
bus interface
bridge memory

I/O bus Expansion slots for

other devices such
USB graphics disk as network adapters.
controller adapter controller

mouse keyboard monitor

– 25 –
disk CS 105
Reading a Disk Sector (1)
CPU chip
CPU initiates disk read by writing
register file
command, logical block number, and
destination memory address to a port
ALU
(address) associated with disk controller

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
– 26 – CS 105
Reading a Disk Sector (2)
CPU chip
Disk controller reads sector and performs
register file
direct memory access (DMA) transfer into
main memory
ALU

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
– 27 – CS 105
Reading a Disk Sector (3)
CPU chip
When the DMA transfer completes, disk
register file
controller notifies CPU with interrupt (i.e.,
asserts special “interrupt” pin on CPU)
ALU

main
bus interface
memory

I/O bus

USB graphics disk

controller adapter controller

mouse keyboard monitor

disk
– 28 – CS 105
Storage Trends
metric 1980 1985 1990 1995 2000 2000:1980

SRAM $/MB 19,200 2,900 320 256 100 190

access (ns) 300 150 35 15 2 150

metric 1980 1985 1990 1995 2000 2000:1980

DRAM $/MB 8,000 880 100 30 1 8,000

access (ns) 375 200 100 70 60 6
typical size(MB) 0.064 0.256 4 16 64 1,000

metric 1980 1985 1990 1995 2000 2000:1980

$/MB 500 100 8 0.30 0.05 10,000

Disk access (ms) 87 75 28 10 8 11
typical size(MB) 1 10 160 1,000 9,000 9,000

– 29 – (Culled from back issues of Byte and PC Magazine) CS 105

CPU Clock Rates

1980 1985 1990 1995 2000 2000:1980

processor 8080 286 386 Pent P-III
clock rate(MHz) 1 6 20 150 750 750
cycle time(ns) 1,000 166 50 6 1.6 750

– 30 – CS 105
The CPU-Memory Gap
The increasing gap between DRAM, disk, and CPU
speeds.

100,000,000
10,000,000
1,000,000
Disk seek time
100,000
DRAM access time
ns 10,000
SRAM access time
1,000
CPU cycle time
100
10
1
1980 1985 1990 1995 2000
year

– 31 – CS 105
Locality
Principle of Locality:
 Programs tend to reuse data and instructions near those
they have used recently, or that were recently referenced
themselves
 Temporal locality: Recently referenced items are likely to be
referenced in the near future
 Spatial locality: Items with nearby addresses tend to be
referenced close together in time

Locality Example: sum = 0;

for (i = 0; i < n; i++)
• Data
sum += a[i];
– Reference array elements in succession return sum;
(stride-1 reference pattern): Spatial locality
– Reference sum each iteration: Temporal locality
• Instructions
– Reference instructions in sequence: Spatial locality
– Cycle through loop repeatedly: Temporal locality
– 32 – CS 105
Locality Example
Claim: Being able to look at code and get qualitative
sense of its locality is key skill for professional
programmer

Question: Does this function have good locality?

int sumarrayrows(int a[M][N])

{
int i, j, sum = 0;

for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
sum += a[i][j];
return sum;
}
– 33 – CS 105
Locality Example
Question: Does this function have good locality?

int sumarraycols(int a[M][N])

{
int i, j, sum = 0;

for (j = 0; j < N; j++)

for (i = 0; i < M; i++)
sum += a[i][j];
return sum;
}

– 34 – CS 105
Locality Example
Question: Can you permute the loops so that the
function scans the 3-d array a[] with a stride-1
reference pattern (and thus has good spatial
locality)?

int sumarray3d(int a[M][N][N])

{
int i, j, k, sum = 0;

for (i = 0; i < N; i++)

for (j = 0; j < N; j++)
for (k = 0; k < M; k++)
sum += a[k][i][j];
return sum;
}

– 35 – CS 105
Memory Hierarchies
Some fundamental and enduring properties of
hardware and software:
 Fast storage technologies cost more per byte and have less
capacity
 Gap between CPU and main memory speed is widening
 Well-written programs tend to exhibit good locality

These fundamental properties complement each other

beautifully

They suggest an approach for organizing memory and

storage systems known as a memory hierarchy
– 36 – CS 105
An Example Memory Hierarchy
Smaller, L0:
faster, registers CPU registers hold words retrieved
and from L1 cache
costlier L1: on-chip L1
(per byte) cache (SRAM) L1 cache holds cache lines
storage retrieved from the L2 cache memory
devices L2: off-chip L2
cache (SRAM) L2 cache holds cache lines
retrieved from main memory

L3: main memory

Larger, (DRAM)
Main memory holds disk
slower, blocks retrieved from local
and disks
cheaper local secondary storage
L4:
(per byte) (local disks)
storage Local disks hold files
retrieved from disks on
devices remote network servers

L5: remote secondary storage

(distributed file systems, Web servers)

– 37 – CS 105
Caches
Cache: Smaller, faster storage device that acts as
staging area for subset of data in a larger, slower
device
Fundamental idea of a memory hierarchy:
 For each k, the faster, smaller device at level k serves as
cache for larger, slower device at level k+1
Why do memory hierarchies work?
 Programs tend to access data at level k more often than they
access data at level k+1
 Thus, storage at level k+1 can be slower, and thus larger and
cheaper per bit
 Net effect: Large pool of memory that costs as little as the
cheap storage near the bottom, but that serves data to
programs at ≈ rate of the fast storage near the top.

– 38 – CS 105
 Caching in a Memory Hierarchy
Smaller, faster, more expensive
Level k: 8
4 9 14
10 3 device at level k caches a
subset of the blocks from level k+1

Data is copied between

10
4 levels in block-sized transfer
units

0 1 2 3

4 5 6 7 Larger, slower, cheaper storage

Level k+1:
device at level k+1 is partitioned
8 9 10 11 into blocks.

12 13 14 15

– 39 – CS 105
 General Caching Concepts
Program needs object d, which is stored
Request
14
12
12
14
in some block b
0 1 2 3 Cache hit
Level 4*
12 9 14 3  Program finds b in the cache at level
k:
k. E.g., block 14

12
4* Request Cache miss
12
 b is not at level k, so level k cache
must fetch it from level k+1.
E.g., block 12
0 1 2 3  If level k cache is full, then some
Level 4
4* 5 6 7 current block must be replaced
k+1: (evicted). Which one is the “victim”?
8 9 10 11
 Placement policy: where can the new
12 13 14 15 block go? E.g., b mod 4
 Replacement policy: which block
should be evicted? E.g., LRU

– 40 – CS 105
General Caching Concepts
Types of cache misses:
 Cold (compulsory) miss
 Cold misses occur because the cache is empty
 Conflict miss
 Most caches limit blocks at level k to a small subset (sometimes
a singleton) of the block positions at level k+1
 E.g. block i at level k+1 must be placed in block (i mod 4) at
level k
 Conflict misses occur when the level k cache is large enough,
but multiple data objects all map to the same level k block
 E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every time
 Capacity miss
 Occurs when the set of active cache blocks (working set) is
larger than the cache

– 41 – CS 105
Examples of Caching in the
Hierarchy
Cache Type What Cached Where Cached Latency Managed
(cycles) By
Registers 4-byte word CPU registers 0 Compiler
TLB Address On-Chip TLB 0 Hardware
translations
L1 cache 32-byte block On-Chip L1 1 Hardware
L2 cache 32-byte block Off-Chip L2 10 Hardware
Virtual 4-KB page Main memory 100 Hardware+
Memory OS
Buffer cache Parts of files Main memory 100 OS
Network buffer Parts of files Local disk 10,000,000 AFS/NFS
cache client
Browser cache Web pages Local disk 10,000,000 Web
browser
Web cache Web pages Remote server 1,000,000,000 Web proxy
disks server

– 42 – CS 105