Scribd Logo
Upload

Welcome to Scribd!

  • 53 views

    Design and Development of Testbench of

    Uploaded by

    M
    This document describes the design and development of a testbench for a FIFO module. It outlines the objectives which are to learn SystemVerilog, gain understanding of FIFO architecture, design a configurable FIFO, and verify it using UVM. It then discusses the working of FIFOs using pointers, provides a block diagram, and shows the Verilog code for the FIFO design. It also discusses future work such as designing the FIFO in SystemVerilog, developing stimuli for the testbench, and studying high-speed interconnects.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    Design and Development of Testbench of

    Uploaded by

    M
    53 views15 pages
    This document describes the design and development of a testbench for a FIFO module. It outlines the objectives which are to learn SystemVerilog, gain understanding of FIFO architecture, design a configurable FIFO, and verify it using UVM. It then discusses the working of FIFOs using pointers, provides a block diagram, and shows the Verilog code for the FIFO design. It also discusses future work such as designing the FIFO in SystemVerilog, developing stimuli for the testbench, and studying high-speed interconnects.

    Original Title

    Minor_FIFO

    Copyright

    © © All Rights Reserved

    Available Formats

    PPTX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes the design and development of a testbench for a FIFO module. It outlines the objectives which are to learn SystemVerilog, gain understanding of FIFO architecture, design a configurable FIFO, and verify it using UVM. It then discusses the working of FIFOs using pointers, provides a block diagram, and shows the Verilog code for the FIFO design. It also discusses future work such as designing the FIFO in SystemVerilog, developing stimuli for the testbench, and studying high-speed interconnects.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    53 views15 pages

    Design and Development of Testbench of

    Uploaded by

    M
    This document describes the design and development of a testbench for a FIFO module. It outlines the objectives which are to learn SystemVerilog, gain understanding of FIFO architecture, design a configurable FIFO, and verify it using UVM. It then discusses the working of FIFOs using pointers, provides a block diagram, and shows the Verilog code for the FIFO design. It also discusses future work such as designing the FIFO in SystemVerilog, developing stimuli for the testbench, and studying high-speed interconnects.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 15

    DESIGN AND DEVELOPMENT OF

    TESTBENCH OF
    FIFO

    BY : MEET BHANUSHALI (17BEC015)


    NISHITH POSHIYA (17BEC059) 1
    GUIDED BY: Dr. USHA MEHTA
    Outline

    Objective
    Motivation
    Working of FIFO
    Block diagram of FIFO
    Design of FIFO in Verilog
    Future work
    Observations
    Reverences

    2
    Objective

    ⮚ To learn the System Verilog

    ⮚ To gain a better understanding of the architecture of a synchronous FIFO module


    considering various design specifications.

    ⮚ To design a configurable synchronous FIFO module.

    ⮚ To verify the synchronous FIFO module design using UVM.

    ⮚ To validate if the UVM verification environment implemented is thorough in testing


    the synchronous FIFO module functionality with a high level of coverage results.

    3
    Motivation

    ● Widely used in microprocessor and microcontrollers.


    ● Basic building block of any Bus controller module.
    ● Very important module for any IC having different clock domains.
    ● Required attention while we are improving our microprocessors.
    ● Design optimization required according to the operating environment.
    Working of FIFO

    ● FIFOS are implemented using rotating pointers

    ● write and read pointers of a FIFO as head and


    Fig 2. Basic Block diagram of FIFO
    tail of data area

    ● Initially read and write pointers of the FIFO will


    point to the same location

    ● after writing data to 'n'th location, write pointer


    points to 0th location

    Fig.1 FIFO of length 8


    Block Diagram of FIFO

    Fig 2. Basic Block diagram of FIFO


    Design of FIFO in verilog
    module MP1(rd_data,full,empty,clk,rst,wr_en,rd_en,wr_data); //ALWAYS BLOCK
    // MAIN MODULE //WRITE OPERATION
    input clk,rst,wr_en,rd_en; always @(posedge clk or negedge rst)
    input [d_l-1:0]wr_data; begin
    output reg [d_l-1:0]rd_data; if (!full && wr_en)
    output full,empty; begin
    memory[wr_pointer] <= wr_data;
    parameter addr = 8,d_l = 16; wr_pointer <= wr_pointer + 1;
    //WIDTH OF ADDRESS AND DATA end
    reg [addr-1:0]wr_pointer,rd_pointer; else begin
    reg [addr-1:0]memory_status; wr_pointer <= wr_pointer;
    reg [d_l-1:0]memory[addr-1:0]; end
    end
    assign full = (memory_status==(1<<(addr-1)));
    assign empty = (memory_status==0);
    //INITIAL BLOCK
    initial begin
    wr_pointer = 0;
    rd_pointer = 0;
    memory_status = 0;
    end
    code continue…

    //READ OPERATION // MEMORY STATUS


    always @(posedge clk or negedge rst) always @(posedge clk or negedge rst)
    begin begin
    if (!empty && rd_en) if (rd_en && !empty)
    begin memory_status <= memory_status - 1;
    rd_data <= memory[rd_pointer]; else if (wr_en && !full)
    rd_pointer <= rd_pointer + 1;
    memory_status <= memory_status + 1;
    end
    else else
    begin memory_status <= memory_status;
    rd_data <= rd_data; end
    rd_pointer <= rd_pointer;
    end
    end
    Bus interconnect
    QPI network
    PCIe bus
    Future Work

    ● Design of FIFO in System Verilog


    ● Development of FIFO testbench using various stimulus.
    ● Design of high speed interconnect.
    ● Study of PCIe, QPI, SDRAM and DDR SDRAM.
    ● Design of I/O module using FIFO.
    Observations

    ● For effective stimuli generation SV is must.


    ● Depth of FIFO is important parameter for system
    performance.
    ● Can not use FIFO in cross platforms.
    ● For asynchronous FIFO, various control signals must be
    there.
    References

    [1] Miro Panades and A. Greiner. Bi-synchronous FIFO for synchronous circuit
    communication well suited for network-on-chip in GALS architectures. In First
    International Symposium on Networks-on-Chip (NOCS’07), pages 83–94, May 2007.

    [2] M. A. Khan and A. Q. Ansari. n-Bit multiple read and write FIFO memory model
    for network-on-chip. In 2011 World Congress on Information and Communication
    Technologies, pages 1326–1331, December 2011.

    [3] http://www.asic-world.com/examples/vhdl/syn_fifo.html

    [4] https://www.electronicsforu.com/electronics-projects/software-projects-ideas/fifo-
    design-using-verilog
    THANK YOU

    You might also like