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Technical Proficiency Andtraining-1 Vlsi: Minor Project-1 On PWM Generator With Variable Duty Cycle

This document describes a project to implement a pulse width modulation (PWM) generator with variable duty cycle using Verilog. The PWM generator creates a 10MHz PWM signal whose duty cycle can be increased or decreased in 10% increments using two buttons. The Verilog code for the PWM generator and test bench are included, and the project is simulated using ISE Design Suite 14.7 to demonstrate a PWM output with changing duty cycle.

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Ram M
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210 views18 pages

Technical Proficiency Andtraining-1 Vlsi: Minor Project-1 On PWM Generator With Variable Duty Cycle

This document describes a project to implement a pulse width modulation (PWM) generator with variable duty cycle using Verilog. The PWM generator creates a 10MHz PWM signal whose duty cycle can be increased or decreased in 10% increments using two buttons. The Verilog code for the PWM generator and test bench are included, and the project is simulated using ISE Design Suite 14.7 to demonstrate a PWM output with changing duty cycle.

Uploaded by

Ram M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Technical

Proficiency
andTraining-1
VLSI
MINOR PROJECT-1
On
PWM GENERATOR WITH  Variable
Duty Cycle
Abstract

• This project demonstrates how a simple and fast pulse width modulator (PWM)
generator can be implemented using Verilog programming. It is simulated using

• ISE Design Suite 14.7

• The Verilog PWM (Pulse Width Modulation) generator creates a 10MHz PWM
signal with variable duty cycle. Two buttons which are debounced are used to
control the duty cycle of the PWM signal. The first push button is to increase the
duty cycle by 10%, and the other button is to decrease the duty cycle by 10%.
Contents
• INTRODUCTION
• METHODOLOGY
• IMPLEMENTATION
• RESULTS
• CONCLUSION
• REFERENCES
Introduction

• PWM is a modulation technique, which converts analog signal into a


digital signal for transmission.

• PWM converts an audio signal into a sequence of pulses having


constant amplitude, but the width is proportional to amplitude of an
audio signal.
DUTY CYCLE:

The percentage of time in which the PWM signal remains HIGH (on time) is

called as duty cycle. If the signal is always ON it is in 100% duty cycle and if it

is always off it is 0% duty cycle. The formulae to calculate the duty cycle is

shown below.

Duty Cycle =Turn ON time/ (Turn ON time + Turn OFF time)


Methodology
Implementation
module PWM_Generator_Verilog
(
clk,
increase_duty,
decrease_duty,
PWM_OUT
);
input clk;
input increase_duty;
input decrease_duty;
output PWM_OUT;
wire slow_clk_enable;
reg[27:0] counter_debounce=0;
wire tmp1,tmp2,duty_inc;
wire tmp3,tmp4,duty_dec;
reg[3:0] counter_PWM=0;
reg[3:0] DUTY_CYCLE=5;
always @(posedge clk)
begin
counter_debounce <= counter_debounce + 1;
if(counter_debounce>=1)
counter_debounce <= 0;
end
assign slow_clk_enable = counter_debounce == 1 ?1:0;
DFF_PWM PWM_DFF1(clk,slow_clk_enable,increase_duty,tmp1);
DFF_PWM PWM_DFF2(clk,slow_clk_enable,tmp1, tmp2);
assign duty_inc = tmp1 & (~ tmp2) & slow_clk_enable;
DFF_PWM PWM_DFF3(clk,slow_clk_enable,decrease_duty, tmp3);
DFF_PWM PWM_DFF4(clk,slow_clk_enable,tmp3, tmp4);
assign duty_dec = tmp3 & (~ tmp4) & slow_clk_enable;
always @(posedge clk)
begin
if(duty_inc==1 && DUTY_CYCLE <= 9)
DUTY_CYCLE <= DUTY_CYCLE + 1;
else if(duty_dec==1 && DUTY_CYCLE>=1)
DUTY_CYCLE <= DUTY_CYCLE - 1;
end
always @(posedge clk)
begin
counter_PWM <= counter_PWM + 1;
if(counter_PWM>=9)
counter_PWM <= 0;
end
assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0;
endmodule

module DFF_PWM(clk,en,D,Q);
input clk,en,D;
output reg Q;
always @(posedge clk)
begin
if(en==1)
Q <= D;
end
endmodule
Test bench
module tb_PWM_Generator_Verilog;
// Inputs
reg clk;
reg increase_duty;
reg decrease_duty;
// Outputs
wire PWM_OUT;
// Instantiate the PWM Generator with variable duty cycle in Verilog
PWM_Generator_Verilog PWM_Generator_Unit(
clk(clk),
increase_duty(increase_duty),
decrease_duty(decrease_duty),
PWM_OUT(PWM_OUT)
);
// Create 100Mhz clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
increase_duty = 0;
decrease_duty = 0;
#100;
increase_duty = 1;
#100;// increase duty cycle by 10%
increase_duty = 0;
#100;
increase_duty = 1;
#100;// increase duty cycle by 10%
increase_duty = 0;
#100;
increase_duty = 1;
#100;// increase duty cycle by 10%
increase_duty = 0;
#100;
decrease_duty = 1;
#100;//decrease duty cycle by 10%
decrease_duty = 0;
#100;
decrease_duty = 1;
#100;//decrease duty cycle by 10%
decrease_duty = 0;
#100;
decrease_duty = 1;
#100;//decrease duty cycle by 10%
decrease_duty = 0;
end
endmodule
Results
Conclusion

In a nutshell the project is all about generation of PWM signals with varying duty
cycle using Verilog code and tested on ISE10.1 XILINX is used as software. The
comparator is necessary to compare between the data available in register and
counter to generate suitable PWM signals. The generated PWM signals have a fixed
frequency depended on the frequency of square wave, and a variable duty cycle that
changes from 0% to 100%. These signals can be used to drive a BLDC motor.
References

 https://www.fpga4student.com/2017/08/verilog-code-for-pwm-generator.html

 https://ieeexplore.ieee.org/document/7755586

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