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Lession 6

This document summarizes key concepts related to strengths, data types, scalars, vectors, parameters, and memories in Verilog. It includes 4 illustrations of how signal strengths determine output values when multiple drivers are present. It also includes code examples of modules using buffers with different strengths and a wand gate. Verilog supports different data types including scalars and vectors. Memories are classified and parameters allow customizable values in Verilog code.

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Neralla Manikanta
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57 views12 pages

Lession 6

This document summarizes key concepts related to strengths, data types, scalars, vectors, parameters, and memories in Verilog. It includes 4 illustrations of how signal strengths determine output values when multiple drivers are present. It also includes code examples of modules using buffers with different strengths and a wand gate. Verilog supports different data types including scalars and vectors. Memories are classified and parameters allow customizable values in Verilog code.

Uploaded by

Neralla Manikanta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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GMR Institute of Technology

Name: Dr. Jami Venkata Suman


Department: ECE
Designation: Assistant Professor
Title: Strengths, Data types, Scalars &
Vectors, Parameters, Memory, Strings

1
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STRENGTHS
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• Illustration1: If a signal line a is driven by two sources – b at
1 level with strength strong1” and c at level 0 with strength
“pull0”– a will take the value 1. 
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• Illustration2: If a signal line a is driven by two sources – b at


1 level with strength “pull1” and c at level 0 with strength
“strong0” a will take the value 0.

• Illustration3: If a signal line a is driven by two sources – b at


1 level with strength strong1” and c at level 0 with strength
“strong0” a will take the value x (indeterminate).

• Illustration4: If a signal line a is driven by two sources – b


at 1 level with strength “weak1” and c at level 0 with strength
“large0” a will take the value 0.
module contres (o,i1,i2);
input i1,i2;
output o;
buf(supply1,pull0)g1(o,i1), g2(o,i2)
endmodule
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module contres1(o,i1,i2);
input i1,i2;
output o;
buf(strong1 ,pull0)g1(o,i1);
buf(pull1,pull0)g2(o,i2);
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endmodule
module wand1(i1,i2,o);
input i1,i2;
output o;
wand o;
buf(strong1,pull0)g1(o,i1);
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buf(pull1,pull0)g2(o,i2);
endmodule
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DATA TYPES IN VERILOG
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SCALARS AND VECTORS
CLASSIFICATIONS OF MEMORIES
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GMR Institute of Technology
MEMORIES
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PARAMETERS

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