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Cmos Process Flow

The document describes the CMOS process flow for manufacturing transistors. It discusses design considerations like channel engineering and source/drain engineering to overcome scaling limitations. The CMOS process involves trench isolation, well implantation, gate patterning, halo and extension implants, spacer formation, source/drain implantation, contact etching and metal deposition. Channel engineering techniques like pocket halo and SSRC distributions are used to reduce electric field penetration with scaling. Shallow and deep source/drain implants address parasitic resistance issues at smaller dimensions.

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SHAIK MUSTHAFA
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188 views25 pages

Cmos Process Flow

The document describes the CMOS process flow for manufacturing transistors. It discusses design considerations like channel engineering and source/drain engineering to overcome scaling limitations. The CMOS process involves trench isolation, well implantation, gate patterning, halo and extension implants, spacer formation, source/drain implantation, contact etching and metal deposition. Channel engineering techniques like pocket halo and SSRC distributions are used to reduce electric field penetration with scaling. Shallow and deep source/drain implants address parasitic resistance issues at smaller dimensions.

Uploaded by

SHAIK MUSTHAFA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 25

CMOS Process Flow 1

Content:-
1.Transistor Design Methodology
2.Channel engineering
3.Source and Drain engineering
4.Cmos Process Flow
1.Transistor design Methodology 2
1.Continue……… 3

Design Parameters :-
 L=Channel Length
 Vdd=Supply Voltage
 Tox= Oxide thickness
 N=Doping Concentration
 Xj=Junction Depth
 Channel Engineering
 Source and Drain Engineering
1.Continue……… 4

Circuit Characteristics:-
 Delay (Speed Performance of Circuit):-
1.It is Strongly Depends on Vt/Vdd
2.Delay Decreases if Vt/Vdd<0.4

 Active Power(Pac):-
1.Pac=C(Vdd)2 f

 Standby Power:-
1.Psb=WVdd Ioff
W=width of the transistor(cm)
Ioff =off current(A/cm)
1.Continue……. 5

Reliability and Compactibility :-

 Reliability means how many years it will work

 Compactibility means what is the Supply Voltage is required


2.Channel Engineering 6

 2 Types Process
1)Pocket Halo
2)Super Steep Retrograde Channel (SSRC)

 We Know If We Scale the Technology then Doping Conc increases


Before Scaling After Scaling
Na (or) Nd Scaled by K Na*K (or) Nd*K
2.Continue………. 7

Disadvantages over increasing Doping conc:-

 Effective mobility(ueff) will decreases due Scattering effect at the interface.

 Junction Capacitance will increase so that Delay will be increases


T=CV/I
 Drain electric field will be induced in entire channel region due to high doping.
2.Continue……… 8

 In the below figure-1 Doping concentration increases entirely channel region.


 In the below figure-2 if we see doping concentration along x-axis and y-axis after
scaling the technology constantly increase.
 This is not good for Technology Scaling.

Figure-1 Figure-2
2.continue……… 9
 So to overcome above limitations highly Dope at selected areas like the end channel on
both source and Drain side like given in below figure
 This is avoiding Drain electricfield penetrating in to channel
 This called Pocket Halo.(along Y-Direction)
 Super Steep Retrograde Channel (SSRC) (along X-Direction).
3.Source and Drain Engineering 10

 This type of engineering intelligent can be


applied when Technology Scaling Decreases
the junction Depth(Xj)
 Due to this decreament two disadvantages
occur
1. Parasitic resistance
2. Reliable contact formation
3.continue…….. 11
 To overcome the above limitations
 We have to do doping as given figure
 At the near to gate, junction depth should be less. This is called as “Shallow implant”
 At far from the gate Junction depth should be high. This is called as “Deep implant”
4.CMOS Process Flow 12

1) Trench isolation to define Active Regions


2) Nwell for PMOS transistors
3) Pwell for Nmos transistors
4) Gate oxide formation and gate polysilicon patterning
5) NMOS halo and Shallow extension implant
6) PMOS halo and Shallow extension implant
7) Spacer formation
8) N+ select for NMOS Source/Drain
9) P+ select for PMOS Source/Drain
10) Contact Definition
11) Metal 1 layer patterning
4.1.Trench isolation to define Active Regions 13

 Take a silicon(Si) wafer let a p-type


 Grow oxide every where on Si wafer
 Deposite a Nitride on Oxide layer
 Apply a photo resist by a Active mask using photo lithography
4.1.Continue…… 14
 Etch the Nitride and oxide on the wafer
 And continue the etch si further then trench will form inside silicon
 fill the trench by depositing oxide.
 Clear resist.
 then strip off the nitride and oxide
 After this hole operation the wafer look like this.
4.2.Nwell Mask 15

 Grow oxide on wafer


 Apply photo resist using n-well mask
 Implant Phosphorous ,Antimony
 Clear the photo resist.
4.3.Pwell Mask 16

 Grow oxide on wafer


 Apply photo resist using p-well mask
 Implant Boron ,Indium
 Clear the photo resist
 Diffuse both wells
4.4.Polysilicon Gate mask 17

 Grow the gate oxide on wafer


 Deposit polysilicon on gate oxide
 Apply photo resist using poly mask
 Etch the Polysilicon and oxide
 Clear photo resist
 Then finally stay polysilicon oxide stack or gate stack
4.5.NMOS Halo and Extension 18

 Develop photo resist using N+ select mask


 implant Boron Halo at 45 degree tilt angle
 implant Arsenic shallow extension
 Clear the photo resist
 Halo ->1012-1013/cm2 ,Extension-> 1014-1015/cm2
4.6.PMOS Halo and Extension 19

 Develop photo resist using P+ select mask


 implant Phosphorous Halo at 45 degree tilt angle
 implant Boron shallow extension 0 degree
 Clear the photo resist
4.7.Spacer Formation 20

 Cover entire wafer with oxide


 On oxide cover with nitride
 Etch nitride by Anisotropically then we left with Spacer form given above.
 Anisotropic etch done only in vertical direction.
4.8.N+ select mask 21

 N+ needs deep Arsenic implant


 Develop photo resist using N+ select mask
 Implant arsenic bcz it has higher energy.
 So finally wafer look like in the above figure.
4.9.P+ Select mask 22

 Develop Photo Resist using P+ select mask


 Implant Boron
 Clear photo resist
 Annealing the source / drain bcz if any damaze happens inside silicon.
4.10.Contact Mask 23

 We have to make contact for Gate ,Source and Drain.


 Deposite oxide
 Develop photo resist using contact mask
 Etch the contact hole
 Deposit contact plugs in holes
 Take this plugin setup in to next phase.
4.11.Metal-1 mask 24

 Deposit metal every where


 Develop photo resist using metal mask
 Then Etch the metal
 Clear photo resist
 Finally cmos process model device look like as given above.
25

THANK YOU…………

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