Control Unit Operation

Dr Wajid Aziz 1
 Functional Requirements
• Functions of Control Unit

– The control unit performs two basic tasks.

• Sequencing
– Causing the CPU to step through a series of micro-
operations

• Execution
– Causing the performance of each micro-op (generates
control signals)

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 Micro-Operations
• A computer executes a program.
• The program consists of sequence of instruction.
• The operation of computer involves execution of programs
consisting of sequence of instruction cycles with one
machine instruction per cycle.
• An execution may consists of fetch, indirect, execute and
interrupt cycles.
• Each cycle is made up of a sequence of more fundamental
or atomic operations called micro operation.
• A single micro-operation generally involves
– A transfer between registers
– A transfer between register and external bus, or
– Simple ALU operation.

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Constituent Elements of Program
Execution

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 The Fetch Cycle
The fetch cycle occurs at the beginning of each instruction cycle and causes
the instruction to be fetched from memory. Four registers are involved:
• Memory Address Register (MAR)
– Connected to address bus
– Specifies address for read or write op
• Memory Buffer Register (MBR)
– Connected to data bus
– Holds data to write or last data read
• Program Counter (PC)
– Holds address of next instruction to be fetched
• Instruction Register (IR)
– Holds last instruction fetched

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 Fetch Sequence
• Address of next instruction is in PC
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data bus
• Data from data bus is copied into MBR
• PC incremented by 1 (in parallel with data fetch
from memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches

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 Fetch Sequence (Symbolic)
The simple fetch cycle actually consists of three steps and
four micro-operations. Each Micro-operation involves the
movement of data into or out of a register. Symbolically,
the sequence of events can be written as:

• t1: MAR <- (PC)

• t2: MBR <- (memory)
• PC <- (PC) +1
• t3: IR <- (MBR)
or
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• t3: PC <- (PC) +1
• IR <- (MBR)
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 Rules for Clock Cycle Grouping
• Proper sequence must be followed
– MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
– Must not read & write same register at same
time
– MBR <- (memory) & IR <- (MBR) must not be
in same cycle
• Also: PC <- (PC) +1

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 The Indirect Cycle
If the instruction specifies an indirect address,
then an indirect cycle must precede the
execute cycle.
• MAR <- (IRaddress) - address field of IR
• MBR <- (memory)
• IRaddress <- (MBR)

• MBR contains an address

• IR is now in same state as if direct
addressing had been used.
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 The Interrupt Cycle
A simple sequence of events for interrupt cycle is

• t1: MBR <-(PC)

• t2: PC <- routine-address

• This is a minimum
– May take more additional micro-ops to get addresses
– Saving context is done by interrupt handler routine, not
micro-ops

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 The Execute Cycle
• The fetch, indirect and interrupt cycles are simple and
predictable and have fixed set of micro-operations.
• However for execute cycle there N different micro-
operations for N different Opcodes.
• Consider the an add instruction
ADD R1,X
• Add the contents of location X to Register R1.
• The following micro-operations might occur.
– t1: MAR <- (IRaddress)
– t2: MBR <- (memory)
– t3: R1 <- R1 + (MBR)
• No overlap of micro-operations

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 Instruction Cycle
• Each phase decomposed into sequence of
elementary micro-operations
• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
– One sequence of micro-operations for each opcode
• Need to tie sequences together
• Assume new 2-bit register
– Instruction cycle code (ICC) designates which part of
cycle processor is in
• 00: Fetch
• 01: Indirect
• 10: Execute
• 11: Interrupt

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Flowchart for Execution Cycle

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 Control of the Processor
• Functional Requirements
– Functional requirements for control unit are
defined as the functions that control unit must
perform .
– Following three step process leads to the
characterization of Control Unit.

• Define the basic elements of processor

• Describe micro-operations processor performs
• Determine functions control unit must perform

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 Functional Requirements
• Basic Elements of a • Types of Micro
Processor Operations

– ALU – Transfer data between

– Registers registers
– Internal data pahs – Transfer data from register
– External data paths to external
– Control Unit – Transfer data from
external to register
– Perform arithmetic or
logical ops

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Model of Control Unit

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 Control Signals
• Clock
– This is how control unit “keeps time”.
– One micro-instruction (or set of parallel micro-instructions) per clock
cycle

• Instruction register
– Op-code for current instruction
– Determines which micro-instructions are performed

• Flags
– State of CPU
– Results of previous operations

• Control Signals From control bus

– Interrupts
– Acknowledgements

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 Control Signals - output
• Control Signals Within CPU
– Cause data movement
– Activate specific ALU functions

• Control Signals to CPU Control Bus

– To memory
– To I/O modules

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 Control Systems
• Two types of control systems
– Micro-Programmed Control Systems
– Hardwired Control Systems
Hardwired & Microprogrammed
• Hardwired Control Unit: When the control
signals are generated by hardware using
conventional logic design techniques, the
control unit is said to be hardwired.
• Micro programmed control unit: A control
unit whose binary control variables are
stored in memory is called a micro
programmed control unit.
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 Microprogrammed
• Control Memory: Control Memory is the
storage in the microprogrammed control unit
to store the microprogram

• Control Word: The control variables at any

given time can be represented by a control
word string of 1 's and 0's called a control
word.
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Organization
of
Control
Memory
• The general configuration of a micro-programmed control unit is demonstrated
in the block diagram of Fig 1

The control memory is assumed to be a ROM, within which all control

information is permanently stored.

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 Address Sequencing
 Microinstructions are stored in control memory in groups, with each group
specifying a routine.
 To appreciate the address sequencing in a micro-program control unit, let us
specify the steps that the control must undergo during the execution of a single
computer instruction.
Step-1:
 An initial address is loaded into the control address register when power is turned
on in the computer.
 This address is usually the address of the first microinstruction that activates the
instruction fetch routine.
 The fetch routine may be sequenced by incrementing the control address register
through the rest of its microinstructions.
 At the end of the fetch routine, the instruction is in the instruction register of the
computer.

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 Cont…
• Step-2:  The control memory next must go through the routine that
determines the effective address of the operand.
•  A machine instruction may have bits that specify various addressing
modes, such as indirect address and index registers.
•  The effective address computation routine in control memory can be
reached through a branch microinstruction, which is conditioned on the status
of the mode bits of the instruction.
•  When the effective address computation routine is completed, the address
of the operand is available in the memory address register.

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• Step-3:  The next step is to generate the microoperations that execute the instruction fetched from
memory.
•  The microoperation steps to be generated in processor registers depend on the operation code part
of the instruction.
•  Each instruction has its own micro-program routine stored in a given location of control memory.
•  The transformation from the instruction code bits to an address in control memory where the
routine is located is referred to as a mapping process.
•  A mapping procedure is a rule that transforms the instruction code into a control memory address.
• Step-4:
•  Once the required routine is reached, the microinstructions that execute the instruction may be
sequenced by incrementing the control address register.  Micro-programs that employ subroutines
will require an external register for storing the return address.
•  Return addresses cannot be stored in ROM because the unit has no writing capability.  When the
execution of the instruction is completed, control must return to the fetch routine.
•  This is accomplished by executing an unconditional branch microinstruction to the first address of
the fetch routine.

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 Control Unit Organization

Sequencing Logic Module

• Generates the address of the next
microinstructions.
•Loads MAR

Control Logic Module

• Generates control signals
 Functioning of
Microprogrammed
Control Unit
Microinstruction Classification

Vertical microprogramming
 Each microinstruction specifies a single (or few) micro-
operations to be performed
• Limited ability to express parallelism

Horizontal microprogramming
 Each microinstruction specifies many different micro-
operations to be performed in parallel.
• Wide memory word
• High degree of parallel operations are possible
 Micro-Program Control
• Advantages
– Only thing that needs to be modified is the
micro-code. No hardware modification is needed.
– Microprogramming is flexible and easy to
design.
– Allows for convenient hardware/software trade
offs. If something you want is not implemented
in hardware it can be implemented in software.
 Micro-Program Control
• Disadvantages
– All instructions must go through an additional
level of interpretation, slowing down the
program execution.
– Development is expensive due to software
tools.
• Hardwired Control Unit

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 Hard Wired Control Unit
• The Cycles (Fetch, Indirect, Execute,
Interrupt) are constructed as a State
Machine

• The Individual instruction executions can

be constructed as State Machines
 State Machine

•Combinational logic
– Determine outputs at each state.
– Determine next state.
•Storage elements
– Maintain state representation. Store the value of logical signals

State Machine

Inputs Combinational Outputs

Logic Circuit

Storage
Clock Elements
Cont…..
• Logical Gates & Boolean Expressions
– AND, OR, NOT, NAND, XOR etc
• In hardwired control, fixed logic circuits that
correspond directly to the Boolean expressions are
used to generate the control signals
• Clearly hardwired control is faster than
microprogrammed control. However, hardwired
control could be very expensive and complicated for
complex systems
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 Example State Machine

Inputs

Outputs

Next States
Example

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 Problems With Hard Wired
Designs
• Complex sequencing & micro-operation
logic
• Difficult to design and test
• Inflexible design
• Difficult to add new instructions