Basic I/O Interface

Barry B. Brey
[email protected]

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  The instructions used with I/O are IN and OUT.
 The IN instruction input data from an external I/O
device to the accumulator.
 The OUT instruction copies the contents of the
accumulator out to an external I/O device.
 The accumulator is AL (8-bit I/O), AX (16-bit I/O)
or EAX (32-bit I/O).

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  As with memory, I/O devices have I/O addresses
or, as Intel at times refers to them, I/O port
addresses. The port address appears on address
bus bits A15-A0 and is a 16-bit address. This
allows I/O devices at addresses 0000H-FFFFH.
 There are two ways to specify an I/O port address.
(1) an 8-bit immediate address and (2) a 16-bit
address located in register DX.
 The 8-bit I/O port address are 0000H-00FFH and
the 16-bit addresses are 0000H-FFFFH.

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  I/O can be either isolated or memory mapped.
Isolated I/O uses the IN and OUT instructions and
has its own I/O ports addresses of 0000H-FFFFH.
Memory mapped I/O uses a portion of the memory
map for I/O and any memory reference instruction.
 Most Intel-based systems use isolated I/O. An
example memory-mapped system is the Apple
Macintosh and its PowerPC microprocessor.

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 I/O
Isolated

I/O
Memory
Mapped

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  The PC I/O space mainly exists at locations below
I/O port 0400H.
 Main board devices appear at addresses 0000H
through 00FFH.
 Early ancillary I/O devices appear at I/O locations
0100H through 03FFH.
 Modern components appear at I/O locations above
0400H.
 The slide on the next page shows many of the I/O
devices found in the personal computer.

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 I/O map in a PC
showing many of the
fixed areas of I/O

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  The IN instruction primarily takes the following
forms:

IN AL,23H ;immediate
IN AL,DX ;DX holds address
IN AX,44H
IN AX,DX
IN EAX,2AH
IN EAX,DX

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  The OUT instruction primarily takes the following
forms:

OUT 23H,AL ;immediate

OUT DX,AL ;DX holds port
OUT 4CH,AX
OUT DX,AX
OUT 1EH,EAX
OUT DX,EAX

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  String I/O uses either INS or OUTS, but these are
rarely used in programs.
 INSB, INSW, INSD are acceptable forms of INS.
 OUTSB, OUTSW, and OUTSD are acceptable forms
of OUTS.

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  To send a 00H to I/O port 62H

MOV AL,00H
OUT 62H,AL

or

MOV AL,00H
MOV DX,62H
OUT DX,AL

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  To input a number for I/O address 71H use the
following:

IN AL,71H

or

MOV DX,71H
IN AL,DX

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  The basic input port connects an external set of
bits to the microprocessor data bus whenever the
microprocessor issues the correct I/O port address
with the IN instruction.
 The next slide illustrates the basic input port
connecting a series of 8 switches to the data bus
during the IN instruction. The SEL signal is
generated for the IN instruction at the desired port.
This circuit does not appear in the drawing.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  To illustrate the basic output port eight LED diodes
are interfaces to a latch that acts as an output port
to catch data sent to it from the OUT instruction.
 As with the input port the logic circuit required to
generate the SEL signal from the port address and
OUT instruction is not shown.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  The parallel port is an example of a device that
requires some handshaking to operate properly.
 The connection on the printer is via a 36-pin
Centronics connector and the connection on the
parallel port is a 25-pin connector.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;An assembly language procedure that prints the ASCII
contents of BL.

PRINT PROC NEAR

.REPEAT ;test the busy flag
IN AL,BUSY
TEST AL,BUSY_BIT
.UNTIL ZERO
MOV AL,BL ;position data in AL
OUT PRINTER,AL ;print data
RET
PRINT ENDP

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  The most basic input device is a switch. Switches
bounce and this is often undesirable. Switches also
do not produce a voltage, but more often present a
logic 0 to a circuit.
 In order to make a switch TTL compatible a pullup
resistor is used as shown in the next slide. The
value should be between 1K and 27K.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  Switches bounce and bounces must be removed
either with software, discussed later, or with
hardware. Although hardware is undesirable
because of the cost.
 The next slide illustrate two techniques used to
remove bounces with hardware. These are little
used today.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  LED diodes are used in many systems as indicators
and as sources of an infrared beam.
 LEDs must be biased because the are not 5.0V
devices.
 A typical (Red, Green, or Yellow) LED requires a
current of 10mA and a voltage of 1.65V.
 A Blue, White, or UltraBright LED requires more
current and may require a greater voltage. A Blue
LED, for example require 30 mA at 2.5 V.
 The next slide show two way to interface a Red LED
to a digital signal.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  Both illustrations use a 330Ω resistor in series with
the LED. Why?
 The voltage dropped across the LED is 1.65V and
the voltage dropped from the collector to the
emitter of the transistor is about 0.1 V when it
conducts. The output of the inverter is likewise
about 0.1 V when at a logic zero.
 This leaves 3.15 V across the resistor and a current
of 10mA through it. Ohms Law determines the
value of the resistor. 3.15V/10mA = 315 Ω.
 The nearest standard resistor values are 310 and
330. I choose the 330, but the 310 will also work
equally well.

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  Circuit (b) uses a 7404 TTL inverter because 10mA
of current is needed to cause the LED to light. A
74LS04 gate only supplies 4.0mA and also does a
74HCT04. About the only currently available TTL
gate that can supply enough current is the 7404
standard gate.
 Circuit (a) uses a transistor in place of the standard
TTL gate. A transistor must be biased for proper
operation.

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  The 2N2222 is a very common NPN transistor (may
be the number?). Another common transistor is
the mps123 (the number?).
 The current gain of this transistor is listed as 100
minimum, 250 typical, and 650 maximum. Always
use the worst-case gain or 100 in this case.
 The bias resistor is meant to connect to a TTL
compatible signal. The logic 1 level is something
between 5.0V and 2.4V. He 2.4V is the worst-case
logic 1 voltage and is used to determine the base
bias resistor value. (2.4V-0.7)/0.1mA = 17K Ω.
An 18K Ω was chosen as the nearest standard
resistor value.

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  Large current loads such as motors or large relays
require a Darlington pair in place of the transistor
driver.
 The next slide shows how to connect a Darlington
pair to drive a 12V motor from a TTL signal.
 The diode is used to prevent the transistor from
being destroyed by the inductive kickback current
that appears when the field collapses in the coil.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  As with memory addresses, port addresses must
also be decoded to select an I/O device for a
particular port number.
 In most embedded systems only the least
significant eight address bits are decoded. In a PC
class system all 16-bits of the I/O address are
decode.
 The next slide shows a simple 8-bit decoder to
decode I/O ports FOH-F7H.

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 Combinational port decoder: Ports F0H to F7H

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 Combinational port decoder using programmable logic:
Ports F0H to F7H
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 library ieee;
use ieee.std_logic_1164.all;

entity DECODER_11_11 is
port (
A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC;
D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC
);
end;

architecture V1 of DECODER_11_11 is
begin
D0 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and not A0 );
D1 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and not A1 and A0 );
D2 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and not A0 );
D3 <= not( A7 and A6 and A5 and A4 and not A3 and not A2 and A1 and A0 );
D4 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and not A0 );
D5 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and not A1 and A0 );
D6 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and not A0 );
D0 <= not( A7 and A6 and A5 and A4 and not A3 and A2 and A1 and A0 );
end V1;

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Combinational port decoder using programmable logic:
Ports EFF8H to EFFFH
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 library ieee;
use ieee.std_logic_1164.all;

entity DECODER_11_12 is
port (
Z, A12, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC;
D0, D1, D2, D3, D4, D5, D6, D7: out STD_LOGIC
);
end;

architecture V1 of DECODER_11_12 is
begin
D0 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and not A2 and not A1 and not A0 );
D1 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and not A2 and not A1 and A0 );
D2 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and not A2 and A1 and not A0 );
D3 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and not A2 and A1 and A0 );
D4 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and A2 and not A1 and not A0 );
D5 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and A2 and not A1 and A0 );
D6 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and A2 and A1 and not A0 );
D7 <= not ( not Z and not A12 and A10 and A9 and A8 and A7 and A6 and A5 and
A4 and A3 and A2 and A1 and A0 );
end V1;

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Banks found in the 8086, 80186, 80286 and 80386SX
microprocessors
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 Decoding two 16-bit ports using
programmable logic:
Port 40H and port 41H

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 library ieee;
use ieee.std_logic_1164.all;

entity DECODER_11_14 is
port (
BHE, IOWC, A7, A6, A5, A4, A3, A2, A1, A0: in STD_LOGIC;
D0, D1: out STD_LOGIC
);
end;

architecture V1 of DECODER_11_14 is
begin
D0 <= BHE or IOWC or A7 or not A6 or A5 or A4 or A3 or A2 or A1 or A0;
D1 <= BHE or IOWC or A7 or not A6 or A5 or A4 or A3 or A2 or A1 or not A0;
end V1;

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Decoding two 16-bit ports using
programmable logic:
Port 64H and port 65H

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 library ieee;
use ieee.std_logic_1164.all;

entity DECODER_11_15 is
port (
IORC, A7, A6, A5, A4, A3, A2, A1: in STD_LOGIC;
D0: out STD_LOGIC
);
end;

architecture V1 of DECODER_11_15 is
begin
D0 <= IORC or A7 or not A6 or not A5 or A4 or A3 or not A2 or A1;
end V1;

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  The only difference between 16-bit wide I/O and
32-bit wide I/O is that 32-bit wide I/O consists of
4 side-by-side 8-bits ports instead of 2.
 The next slide illustrates a 32-bit wide I/O port.

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Decoding four 32-bit ports using
programmable logic:
Ports 70H to 73H

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 library ieee;
use ieee.std_logic_1164.all;

entity DECODER_11_16 is
port (
IORC, A7, A6, A5, A4, A3, A2: in STD_LOGIC;
D0: out STD_LOGIC
);
end;

architecture V1 of DECODER_11_16 is
begin
D0 <= IORC or A7 or not A6 or not A5 or not A4 or A3 or A2;
end V1;

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Decoding two 32-bit ports using
programmable logic:
Ports 2000H and 2001H

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 library ieee;
use ieee.std_logic_1164.all;

entity DECODER_11_17 is
port (
MIO, BE0, BE1, WR, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3: in
STD_LOGIC;
D0, D1: out STD_LOGIC
);
end;

architecture V1 of DECODER_11_17 is
begin
D0 <= MIO or BE0 or not WR or A15 or A14 or not A13 or A12 or A11 or A10 or A9 or A8 or A7
or A6 or A5 or A4 or A3;
D1 <= MIO or BE1 or not WR or A15 or A14 or not A13 or A12 or A11 or A10 or A9 or A8 or A7
or A6 or A5 or A4 or not A3;
end V1;

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  The 8255 PIA is available in DIP or surface mount
forms.
 The 8255 allows the microprocessor to
communicate with the outside world through three
8-bit wide I/O ports.
 The PC uses a few 8255 (in the chip set) to control
the keyboard, speaker, and parallel port.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  Group A is Port A and ½
of Port C (PC7-PC4).
 Group B is Port B and ½
of Port C (PC3-PC0).

A1 A0 Function

0 0 Port A

0 1 Port B

1 0 Port C
1 1 Command Register

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 Interfacing a PPI 8255 to the low bank of a 80386SX microprocessor

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  To program the command register of the 825 and
select operation use command byte A on the prior
slide.
 For example, to program all the ports as outputs
and in mode 0 (most common mode) use:
MOV AL,80H
MOV DX,COMMAND_PORT
OUT DX,AL

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  Mode 0 is the most commonly used mode for
simple inputs and simple latched outputs.
 Mode 1 is used occasionally to provide
handshaking to an I/O device and operate
asynchronously with the device.
 Mode 3 is a bidirectional mode that also includes
handshaking.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 library ieee;
use ieee.std_logic_1164.all;
entity DECODER_11_21 is
port (
IOM, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3,
A2: in STD_LOGIC;
D0: out STD_LOGIC
);
end;
architecture V1 of DECODER_11_17 is
begin
D0 <= not IOM or A15 or A14 or A13 or A12 or A11 or not A10
or not A9 or not A8 or A7 or A6 or A5 or A4 or A3 or A2;
end V1;

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;An assembly language procedure that multiplexes the 8-digit display.
;This procedure must be called often for the display
;to appear correctly.

DISP PROC NEAR USES AX BX DX SI

PUSHF
MOV BX,8 ;load counter
MOV AH,7FH ;load selection pattern
MOV SI,OFFSET MEM-1 ;address display data
MOV DX,701H ;address Port B
;display all 8 digits
.REPEAT
MOV AL,AH ;send selection pattern to Port B
OUT DX,AL
DEC DX
MOV AL,[BX+SI] ;send data to Port A
OUT DX,AL
CALL DELAY ;wait 1.0 ms
ROR AH,1 ;adjust selection pattern
INC DX
DEC BX ;decrement counter
.UNTIL BX == 0
POPF
RET
DISP ENDP

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 //A C++ function that multiplexes the 8-digit display
//uses char sized array MEM
void Disp()
{
unsigned int *Mem = &MEM[0]; //point to array element 0
for ( int a = 0; a < 8; a++ )
{
char b = !( 1 << a ); //form select pattern
_asm
{
mov al,b
mov dx,701H
out dx,al ;send select pattern to Port B
mov al,Mem[a]
dec dx
out dx,al ;send data to Port A
}
Delay(); //wait 1.0 ms
}
}

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 PORTA_ADDRESS EQU 700H ;set port addresses
PORTB_ADDRESS EQU 701H
COMMAND_ADDRESS EQU 703H
;macro to send a command or data to the LCD display
;
SEND MACRO PORTA_DATA, PORTB_DATA, DELAY
MOV AL,PORTA_DATA ;PORTA_DATA to Port A
MOV DX,PORTA_ADDRESS
OUT DX,AL
MOV AL,PORTB_DATA ;PORTB_DATA to Port B
MOV DX,PORTB_ADDRESS
OUT DX,AL
OR AL,00000100B ;Set E bit
OUT DX,AL ;send to Port B
AND AL,11111011B ;Clear E bit
NOP ;a small delay
NOP
OUT DX,AL ;send to Port B
MOV BL,DELAY ;BL = delay count
CALL MS_DELAY ;ms Time Delay
ENDM

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;Program to initialize the LCD display
START:
MOV AL,80H ;Program the 82C55
MOV DX,COMMAND_ADDRESS
OUT DX,AL
MOV AL,0
MOV DX,PORTB_ADDRESS ;Clear Port B
SEND 30H, 2, 16 ;send 30H for 16 ms
SEND 30H, 2, 5 ;send 30H for 5 ms
SEND 30H, 2, 1 ;send 30H for 1 ms
SEND 38H, 2, 1 ;send 38H for 1ms
SEND 8, 2, 1 ;send 8 for 1 ms
SEND 1, 2, 2 ;send 1 for 2 ms
SEND 0CH, 2, 1 ;send 0CH for 1 ms
SEND 6, 2, 1 ;send 6 for 1 ms

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 Programs LCD circuit (L = 1, 8-bit interface) (N = 1, 2-lines) (F = 1, 5 10 characters) (F = 0, 5

Instruction Code Description Time

Clear display 0000 0001 Clears the display and homes the cursor 1.64 ms

Cursor home 0000 0010 Homes the cursor 1.64 ms

Entry mode set 0000 00AS Sets cursor movement direction (A = 1, increment) 40 μs
and shift (S = 1, shift)

Display on/off 0000 1DCB Sets display on/off (D = 1, on) (C = 1, cursor on) 40 μs
(B = 1, cursor blink)

Cursor/display shift 0001 SR00 Sets cursor movement and display shift (S = 1, 40 μs
shift display) (R = 1, right)

Function set 001L NF00 7 characters) 40 μs

Set CGRAM address 01XX XXXX Sets character generator RAM address 40 μs

Set DRAM address 10XX XXXX Sets display RAM address 40 μs

Read busy flag B000 0000 Reads busy flag (B = 1, busy) 0
Write data Data Write data to the display RAM or the character 40 μs
generator RAM

Read data Data Reads data from the display RAM or character 40 μs
generator RAM

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 PORTA_ADDRESS EQU 700H ;set port addresses
PORTB_ADDRESS EQU 701H
COMMAND_ADDRESS EQU 703H
BUSY PROC NEAR USES DX AX
PUSHF
MOV DX,COMMAND_ADDRESS
MOV AL,90H ;program Port A as IN
OUT DX,AL
.REPEAT
MOV AL,5 ;select read from LCD
MOV DX,PORTB_ADDRESS
OUT DX,AL ;and pulse E
NOP
NOP
MOV AL,1
OUT DX,AL
MOV DX,PORTA_ADDRESS
MOV AL,DX ;read busy command
SHL AL,1
.UNTIL !CARRY? ;until not busy
NOV DX,COMMAND_ADDRESS
MOV AL,80H
OUT DX,AL ;program Port A as OUT
POPF
RET
BUSY ENDP

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 WRITE PROC NEAR
MOV AL,BL ;BL to Port A
MOV DX,PORTA_ADDRESS
OUT DX,AL
MOV AL,0 ;write ASCII
MOV DX,PORTB_ADDRESS
OUT DX,AL
OR AL,00000100B ;Set E bit
OUT DX,AL ;send to Port B
AND AL,11111011B ;Clear E bit
NOP ;a small delay
NOP
OUT DX,AL ;send to Port B
CALL BUSY ;wait for completion
RET
WRITE ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 PORT EQU 40H
;An assembly language procedure that controls the stepper motor
STEP PROC NEAR USES CX AX
MOV AL,POS ;get position
OR CX,CX ;set flag bits
IF !ZERO?
.IF !SIGN? ;if no sign
.REPEAT
ROL AL,1 ;rotate step left
OUT PORT,AL
CALL DELAY ;wait 1 ms
.UNTILCXZ
.ELSE
AND CX,7FFFH ;make CX positive
.REPEAT
ROR AL,1 ;rotate step right
OUT PORT,AL
` CALL DELAY ;wait 1 ms
.UNTILCXZ
.ENDIF
.ENDIF
MOV POS,AL
RET
STEP ENDP

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 //A C++ function that controls the stepper motor
char Step(char Pos, short Step)
{
char Direction = 0;
if ( Step < 0 )
{
Direction = 1;
Step =& 0x8000;
}
while ( Step )
{
if ( Direction )
if ( ( Pos & 1 ) == 1 )
Pos = ( Pos >> 1 ) | 0x80;
else
Pos >>= 1;
else
if ( ( Pos & 0x80 ) == 0x80 )
Pos = ( Pos << 1 ) | 1;
else
Pos <<= 1;
_asm
{
mov al,Pos
out 40h, al
}
}
return Pos;
}

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;assembly language version;
;KEY scans the keyboard and returns the key code in AL.
COLS EQU 4
ROWS EQU 4
PORTA EQU 50H
PORTB EQU 51H
KEY PROC NEAR USES CX BX
MOV BL,FFH ;compute row mask
SHL BL,ROWS
MOV AL,0
OUT PORTB,AL ;place zeros on Port B
.REPEAT ;wait for release
.REPEAT
CALL SCAN
.UNTIL ZERO?
CALL DELAY10
CALL SCAN
.UNTIL ZERO?
.REPEAT ;wait for key
.REPEAT
CALL SCAN
.UNTIL !ZERO?
CALL DELAY10
CALL SCAN

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 .UNTIL !ZERO?
MOV CX,00FEH
.WHILE 1 ;find column
MOV AL,CL
OUT PORTB,AL
CALL SHORTDELAY ;see text
CALL SCAN
.BREAK !ZERO?
ADD CH,COLS
ROL CL,1
.ENDW
.WHILE 1 ;find row
SHR AL,1
.BREAK .IF !CARRY?
INC CH
.ENDW
MOV AL,CH ;get key code
RET
KEY ENDP
SCAN PROC NEAR
IN AL,PORTA ;read rows
OR AL,BL
CMP AL,0FFH ;test for no keys
RET
SCAN ENDP

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 //C++ language version of keyboard scanning software
#define ROWS 4
#define COLS 4
#define PORTA 50h
#define PORTB 51h
char Key()
{
char mask = 0xff << ROWS;
_asm {
mov al,0 ;select all columns
out PORTB,al
}
do { //wait for release
while ( Scan( mask ) );
Delay();
}while ( Scan( mask ) );
Do { //wait for key press
while ( !Scan( mask ) );
Delay();
}while ( !Scan( mask ) );
unsigned char select = 0xfe;
char key = 0;
_asm {
mov al,select
out PortB,al
}

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 ShortDelay();
while( !Scan ( mask ) ){ //calculate key code
_asm
{
mov al,select
rol al,1
mov select,al
out PortB,al
}
ShortDelay();
key += COLS;
}
_asm {
in al,PortA
mov select,al
}
while ( ( Select & 1 ) != 0 ) {
Select <<= 1;
key ++;
}
return key;
}

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 bool Scan(mask)
{
bool flag;
_asm
{
in al,PORTA
mov flag,al
}
return ( flag | mask );
}

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;A procedure that reads the keyboard encoder and
;returns the ASCII key code in AL
BIT5 EQU 20H
PORTC EQU 22H
PORTA EQU 20H
READ PROC NEAR
.REPEAT ;poll IBF bit
IN AL,PORTC
TEST AL,BIT5
.UNTIL !ZERO?
IN AL.PORTA ;get ASCII data
RET
READ ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;A procedure that transfers an ASCII character from AH to the printer
;connected to port B
BIT1 EQU 2
PORTC EQU 63H
PORTB EQU 61H
CMD EQU 63H
PRINT PROC NEAR
.REPEAT ;wait for printer ready
IN AL,PORTC
TEST AL,BIT1
.UNTIL !ZERO?
MOV AL,AH ;send ASCII
OUT PORTB,AL
MOV AL,8 ;pulse data strobe
OUT CMD,AL
MOV AL,9
OUT CMD,AL
RET
PRINT ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
  The timer appears in the PC at I/O ports 20H and
23H inside of the chipset. It controls the speaker
and generates a signal to refresh the dynamic
RAM.

A1 A0 Function

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control word

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;A procedure that programs the 8254 timer to function
;as illustrated in Figure 11-34
TIME PROC NEAR USES AX DX
MOV DX,706H ;program counter 0 for mode 3
MOV AL,00110110B
OUT DX,AL
MOV AL,01110100B ;program counter 1 for mode 2
OUT DX,AL
MOV DX,700H ;program counter 0 with 80
MOV AL,80
OUT DX,AL
MOV AL,0
OUT DX,AL
MOV DX,702H ;program counter 1 with 40
MOV AL,40
OUT DX,AL
MOV AL,0
OUT DX,AL
RET
TIME ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;A procedure that controls the speed and direction of the motor
;in Figure 11-40.
;
;AH determines the speed and direction of the motor where
;AH is between 00H and FFH.
CNTR EQU 706H
CNT0 EQU 700H
CNT1 EQU 702H
COUNT EQU 30720
SPEED PROC NEAR USES BX DX AX
MOV BL,AH ;calculate count
MOV AX,120
MUL BL
MOV BX,AX
MOV AX,COUNT
SUB AX,BX
MOV BX,AX
MOV DX,CNTR
MOV AL,00110100B ;program control words
OUT DX,AL
MOV AL,01110100B
OUT DX,AL
MOV DX,CNT1 ;program counter 1
MOV AX,COUNT ;to generate a clear
OUT DX,AL
MOV AL,AH
OUT DX,AL
.REPEAT ;wait for counter 1

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 IN AL,DX
XCHG AL,AH
IN AL,DX
XCHG AL,AH
.UNTIL BX == AX
MOV DX,CNT0 ;program counter 0
MOV AX,COUNT ;to generate a set
OUT DX,AL
MOV AL,AH
OUT DX,AL
RET
SPEED ENDP

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  We often send data asynchronously using the data
in the form illustrated in the next slide.
 Asynchronous data are usually send with one start
bit and one stop bit to frame the data, which is
usually 8-data bits without parity.

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 A2 A1 A0 Function

0 0 0 Receiver buffer (read) and transmitter holding (write)

0 0 1 Interrupt enable

0 1 0 Interrupt identification (read) and FIFO control (write)

0 1 1 Line control

1 0 0 Modem control

1 0 1 Line status

1 1 0 Modem status

1 1 1 Scratch

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 ST P PE Function

0 0 0 No parity

0 0 1 Odd parity

0 1 0 No parity

0 1 1 Even parity

1 0 0 Undefined

1 0 1 Send/receive 1

1 1 0 Undefined

1 1 1 Send/receive 0

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 Baud Rate Divisor Value

110 10,473

300 3840

1200 920

2400 480

4800 240

9600 120

19,200 60

38,400 30

57,600 20

115,200 10

Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;Initialization dialog for Figure 11-45
;Baud rate 9600, 7 data, odd parity, 1 stop
LINE EQU 0F3H
LSB EQU 0F0H
MSB EQU 0F1H
FIFO EQU 0F2H
INIT PROC NEAR
MOV AL,10001010B ;enable Baud rate divisor
OUT LINE,AL

MOV AL,120 ;program Baud 9600

OUT LSB,AL
MOV AL,0
OUT MSB,AL
MOV AL,00001010B ;program 7 data, odd
OUT LINE,AL ;parity, 1 stop
MOV AL,00000111B ;enable transmitter and
OUT FIFO,AL ;receiver
RET
INIT ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;A procedure that transmits AH via the 16650 UART
LSTAT EQU 0F5H
DATA EQU 0F0H
SEND PROC NEAR USES AX
.REPEAT ;test the TH bit
IN AL,LSTAT
TEST AL,20H
.UNTIL !ZERO?
MOV AL,AH ;send data
OUT DATA,AL
RET
SEND ENDP

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 ;A procedure that receives data from the 16550 UART and
;returns it in AL.
LSTAT EQU 0F5H
DATA EQU 0F0H
REVC PROC NEAR
.REPEAT
IN AL,LSTAT ;test DR bit
TEST AL,1
.UNTIL !ZERO?
TEST AL,0EH ;test for any error
.IF ZERO? ;no error
IN AL,DATA
.ELSE ;any error
MOV AL,’?’
.ENDIF
RET
RECV ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 1
Fclk 
1.1RC

Frequency = 1/1.1RC

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ADC PROC NEAR
OUT 40H,AL
.REPEAT ;test INTR
IN AL,42H
TEST AL,80H
.UNTIL ZERO?
IN AL,40H
RET
ADC ENDP

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Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.
 ;Software that records a second of speech and plays it back
;10 times.
;Assumes the clock frequency is 20 MHz on an 80386EX microprocessor
READS PROC NEAR USES ECX DX
MOV ECX,2048 ;count = 2048
MOV DX,700H ;address port 700H
.REPEAT
OUT DX,AL ;start conversion
ADD DX,2 ;address status port
.REPEAT ;wait for converter
IN AL,DX
TEST AL,80H
.UNTIL ZERO?
SUB DX,2 ;address data port
IN AL,DX ;get data
MOV WORDS[ECX-1]
CALL DELAY ;wait for 1/2048 sec
.UNTILCXZ
RET
READS ENDP

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 PLAYS PROC NEAR USES DX ECX
MOV ECX,2048 ;count = 2048
MOV DX,704H ;address DAC
.REPEAT
MOV AL,WORDS[EAX-1]
OUT DX,AL ;send byte to DAC
CALL DELAY ;wait for 1/2048 sec
.UNTILCXZ
RET
PLAYS ENDP
DELAY PROC NEAR USES CX
MOV CX,888
.REPEAT ;waste 1/2048 sec
.UNTILCXZ
RET
DELAY ENDP

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