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A Closer Look at Instruction Set Architectures

This document provides an overview of instruction set architectures and their design. It discusses instruction formats, including the number of operands, instruction length, and memory addressing modes. It also covers endianness and internal storage approaches like stacks versus registers. The key topics are instruction set optimization during design, tradeoffs of instruction length and number of operands, little-endian versus big-endian, and advantages of stacks, accumulators, and general purpose registers for internal storage.
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0% found this document useful (0 votes)
70 views28 pages

A Closer Look at Instruction Set Architectures

This document provides an overview of instruction set architectures and their design. It discusses instruction formats, including the number of operands, instruction length, and memory addressing modes. It also covers endianness and internal storage approaches like stacks versus registers. The key topics are instruction set optimization during design, tradeoffs of instruction length and number of operands, little-endian versus big-endian, and advantages of stacks, accumulators, and general purpose registers for internal storage.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 28

A Closer Look at

Instruction Set Architectures


Lecture Overview

 Introduction
 Instruction formats
• Introduction
• Design Decisions for Instruction Sets
• Little VS Big Endian
• Internal Storage in the CPU
• Number of operands and Instruction Length

2
Introduction

Introduction (1/1)

 We look at different instruction formats,


operand types, and memory access methods.
 We will see the interrelation between
machine organization and instruction formats.
 This leads to a deeper understanding of
computer architecture and organization in
general.

3
Instruction formats

Instruction formats – Introduction (1/2)

 In Chapter (MARIE) we saw that MARIE have an


instruction length of 16 bits and could have, at
most, 1 operand
 In another architecture, those could be different
 So, computer architectures generally differs by
their Instructions Set format.
 An Instruction Set can be described by its
features.

4
Instruction formats

Instruction formats – Introduction (2/2)

 The Instruction set’s features are:


• Number of bits per instruction: 12, 32 and 64 are the most
common
• Type of the CPU elementary memory: Stack-based or
register-based (this will affect the instruction format)
• Number of operands per instruction: Zero, one, two, and
three being the most common.
• Operand location: register-to-register, register to-memory or
memory-to-memory instructions.
• Types of operations: not only types of operations but also
which instructions can access memory and which cannot.
• Type and size of operands: operands can be addresses,
numbers, or even characters.

5
Instruction formats

Design Decisions for Instruction Sets (1/4)

 During the design phase of a computer


architecture, the Instruction set must be
optimized.
• The instruction set must match the architecture.
• It must also maximize the efficiency of the computer
architecture.
 The first thing to define during the design phase is
the instruction set format.
• To understand how this choice is made, we should
know first, how we measure the efficiency of an ISA.

6
Instruction formats

Design Decisions for Instruction Sets (2/4)

 Instruction set architectures are measured


according to:
• Main memory space occupied by a program.
• Instruction complexity: amount of decoding
necessary to execute an instruction (number of
clock cycles per instruction)
• Instruction length (in bits).
• Total number of instructions in the instruction
set.

7
Instruction formats

Design Decisions for Instruction Sets (3/4)

 So, things to consider when designing an


instruction set include:
• Instruction length
- Short Vs long instructions:
→ shorter instructions take up less space in memory 
→ shorter instructions can be fetched quickly 
→ shorter instructions limit the number of instructions 
→ shorter instructions limit the number of operands 
- Variable length VS fixed length instructions:
→ Fixed length instructions are easier to decode 
→ but Fixed length instructions waste space 

8
Instruction formats

Design Decisions for Instruction Sets (4/4)

 Things to consider when designing an instruction set include:


• Number of operands
- Fixed number : Zero, one, two, and three being the most common
- Variable number of operands (even if we have a fixed length instructions):
Expanding opcode (to be explained in this lecture!)
• Addressable registers
- How many? (number of registers)
- How are they stored in the CPU?
• Memory organization
- Word addressable or byte addressable?
- A byte addressable architecture uses little or big endian concept? (to be
explained in this lecture!)
• Addressing modes
- Direct, indirect, immediate, indexed, etc. (to be explained in this lecture!)

9
Lecture Overview

 Introduction
 Instruction formats
• Introduction
• Design Decisions for Instruction Sets
• Little VS Big Endian
• Internal Storage in the CPU
• Number of operands and Instruction Length

10
Instruction formats

Little VS Big Endian (1/5)

 If we have a 32 bit data word, how we store this word


in a byte addressable memory? The Least significant
byte first? Of the most significant byte first?
 Byte ordering, or endianness, is a major architectural
consideration
 We distinguish two concepts for byte ordering:
• Little Endian: A byte with a lower significance is stored in a
lower address
• Big Endian: A byte with a higher significance is stored in a
lower address

11
Instruction formats

Little VS Big Endian (2/5)

 Example 1: consider an integer requiring 4


bytes: Byte 3 Byte 2 Byte 1 Byte 0

• On a little endian machine, this is arranged in


memory as follows:
Base Address + 0 → Byte0
Base Address + 1 → Byte1
Base Address + 2 → Byte2
Base Address + 3 → Byte3

12
Instruction formats

Little VS Big Endian (3/5)

 Example 2: consider an integer requiring 4


bytes: Byte 3 Byte 2 Byte 1 Byte 0

• On a big endian machine, this long integer would


then be stored as:
Base Address + 0 → Byte3
Base Address + 1 → Byte2
Base Address + 2 → Byte1
Base Address + 3 → Byte0

13
Instruction formats

Little VS Big Endian (4/5)

 Example 3: On a byte-addressable machine,


the 32-bit (8 numbers*4 each hex. Decimal number in binary) hex H

value 12345678 is stored at address 0. How is s


th
e
this value stored in memory if the machine h
w
uses a Big Endian concept? A little Endian (l

concept?
• Answer:

14
Instruction formats

Little VS Big Endian (5/5)

 Advantages of Big Endian:


• Is more natural: The most significant byte comes first
(lower address).
• The sign of the number can be determined by looking
at the byte at address offset 0.
• Strings and integers are stored in the same order.
 Advantages of Little Endian:
• Makes it easier to place values on non-word
boundaries.
• High-precision arithmetic is fast and easy.

15
Lecture Overview

 Introduction
 Instruction formats
• Introduction
• Design Decisions for Instruction Sets
• Little VS Big Endian
• Internal Storage in the CPU
• Number of operands and Instruction Length

16
Instruction formats

Internal Storage in the CPU: Stacks VS Registers (1/5)

 Another consideration for architecture design


concerns how the CPU will store data.
 We have three choices:
• A stack architecture.
• An accumulator architecture.
• A general purpose register architecture.
 Designers choosing an ISA must decide which
will work best in a particular environment and
examine the tradeoffs carefully

17
Instruction formats

Internal Storage in the CPU: Stacks VS Registers (2/5)

 Stack Architecture
• A stack is used to execute instructions
• Instructions and operands are implicitly taken from
the stack
• Advantages
- Good code density
- Simple model for evaluation of expressions
• Disadvantages
- A stack cannot be accessed randomly
- Difficult to generate efficient code

18
Instruction formats

Internal Storage in the CPU: Stacks VS Registers (3/5)

 Accumulator architectures
• One operand of a binary operation is implicitly in
the accumulator
- Example: MARIE
• Advantages
- Reduce the internal complexity of the machine
- Allow very short instructions
• Disadvantages
- Memory traffic is very high (since one operand is in
memory)

19
Instruction formats

Internal Storage in the CPU: Stacks VS Registers (4/5)

 General purpose register architectures (GPR)


• General purpose registers can be used instead of
memory
• Advantages
- Registers are faster than memory
- Easy for compilers to deal with
- Can be used very effectively and efficiently
• Disadvantages
- Long Instructions, long fetch and decode times

20
Instruction formats

Internal Storage in the CPU: Stacks VS Registers (5/5)

 General purpose register architectures (GPR)


• GPR are the most widely accepted models for
machine architectures today
• There are three types of GPR
- Memory-memory architectures: may have two or three
operands in memory, allowing an instruction to perform an
operation without requiring any operand to be in a register.
- Register-memory architectures: require a mix, where at
least one operand is in a register and one is in memory.
- Load-store architectures: require data to be moved into
registers before any operations on that data are performed.

21
Lecture Overview

 Introduction
 Instruction formats
• Introduction
• Design Decisions for Instruction Sets
• Little VS Big Endian
• Internal Storage in the CPU
• Number of operands and Instruction Length

22
Instruction formats

Number of operands and Instruction Length (1/6)

 On current architectures, instructions can be


formatted in two ways:
• Fixed length: Wastes space but is relatively fast.
• Variable length: Complex to decode but saves storage
space.
 In this course, we will be interested in Fixed length
instructions.
 In such instructions, we define the maximum
number of operands (this number has a direct
impact on the length of the instruction itself)

23
Instruction formats

Number of operands and Instruction Length (2/6)

 Example:
• MARIE uses a fixed-length instruction with a 4-bit
opcode and 12-bit operand.
• In MARIE the maximum number of operands is
one. Though, some instructions for MARIE have
no operand (for instance: halt).

24
Instruction formats

Number of operands and Instruction Length (3/6)

 The most common instruction formats include zero, one,


two, or three operands:
• Zero operand
- OPCODE only
• One operand (usually a memory address)
- OPCODE + 1 Address
• Two operands (usually registers, or one register and one
memory address)
- OPCODE + 2 Addresses
• Three operands (usually registers, or combinations of registers
and memory)
- OPCODE + 3 Addresses

25
Instruction formats

Number of operands and Instruction Length (4/6)

 Machine instructions that have no operands


must use a stack
 In architectures based on stacks, most
instructions consist of opcodes only; however,
there are special instructions that have just
one operand:
• Push X places the data value found at memory
location X onto the stack
• Pop X removes the top element in the stack and
stores it at location X

26
Instruction formats

Number of operands and Instruction Length (5/6)

 Example: Suppose we wish to evaluate the


following expression: Z = (X x Y) + (W x U)
 The assembly code would be:
For a Three operand ISA For a Two operand ISA For a one operand ISA
(such as MARIE!)
Mult R1, X, Y Load R1, X Load X
Mult R2, W, U Mult R1, Y Mult Y
Add Z, R2, R1 Load R2, W Store Temp
Mult R2, U Load W
Add R1, R2 Mult U
Store Z, R1 Add Temp
Store Z

27
Instruction formats

Number of operands and Instruction Length (6/6)

 Example: Suppose we wish to evaluate the


following expression: Z = (X x Y) + (W x U)
• In a stack architecture the assembly code would
be : Stack
Stack Push Y Y
X
X
For a zero operand ISA
Mult
Push X
Push Y Stack
Mult XxY
Stack
Push W XxY+WxU Push W;
Push U
Push U
Mult Stack
Add Add
Stack U
Store Z
WxU Mult W
XxY WxU

28

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