Scribd
Upload
53 views31 pages

Class: Bsse Semester 4 Credit Hours (3+1) : Ajaz Khan Baig

The document discusses key concepts from an operating systems lecture, including direct memory access (DMA), storage structure, caching, and various protection mechanisms. It covers CPU protection using dual-mode operation with user and monitor modes. Memory protection uses base and limit registers to define valid memory ranges. Caching improves performance by copying frequently used data to faster memory. Networks can be local or wide area.

Uploaded by

lovely person
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
53 views31 pages

Class: Bsse Semester 4 Credit Hours (3+1) : Ajaz Khan Baig

The document discusses key concepts from an operating systems lecture, including direct memory access (DMA), storage structure, caching, and various protection mechanisms. It covers CPU protection using dual-mode operation with user and monitor modes. Memory protection uses base and limit registers to define valid memory ranges. Caching improves performance by copying frequently used data to faster memory. Networks can be local or wide area.

Uploaded by

lovely person
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 31

OPERATING SYSTEM

AJAZ KHAN BAIG

Class : BSSE SEMESTER 4


Credit Hours ( 3+1)
Lecture 4

BOOK:
Operating System Concepts
by Silberschatz and Galvin , 8th Edition

2
 DMA (direct memory access)
 Storage Structure
 Caching
 Protection
 Memory protection
 Process protection
 I/O protection
 H/w Protection
 Network structure
 LAN
 WAN

3
 Used for high-speed I/O devices able to transmit information at close to
memory speeds.

 Device controller transfers blocks of data from buffer storage directly


to main memory without CPU intervention.

 Only one interrupt is generated per block, rather than the one interrupt
per byte.
4
 Used to avoid programmed I/O (one byte at a time) for large data movement
 Requires DMA controller
 Bypasses CPU to transfer data directly between I/O device and memory
 OS writes DMA command block into memory
› Source and destination addresses
› Read or write mode
› Count of bytes
› Writes location of command block to DMA controller
› Bus mastering of DMA controller – grabs bus from CPU
 Cycle stealing from CPU but still much more efficient
› When done, interrupts to signal completion
 Version that is aware of virtual addresses can be even more efficient - DVMA

5
6
 Main memory – only large storage media that the CPU can access directly.

 Secondary storage – extension of main memory that provides large nonvolatile


storage capacity.

 Magnetic disks – rigid metal or glass platters covered with magnetic recording
material

 Disk surface is logically divided into tracks, which are subdivided into
sectors.
 The disk controller determines the logical interaction between the device and
the computer.

7
8
 Storage systems organized in hierarchy.
 Speed
 Cost
 Volatility
 Caching – copying information into faster storage system;
 main memory can be viewed as a last cache for secondary storage.

9
10
› Use of high-speed memory to hold recently-accessed data.

› Requires a cache management policy.

› Caching introduces another level in storage hierarchy.

› This requires data that is simultaneously stored in more than one


level to be consistent.

11
 Migration of A From Disk to Register

12
13
14
15
› Dual-Mode Operation

› I/O Protection

› Memory Protection

› CPU Protection
16
 Sharing system resources requires operating system to ensure that an incorrect
program cannot cause other programs to execute incorrectly.

 Provide hardware support to differentiate between at least two modes of


operations.

 User mode – execution done on behalf of a user.


 Monitor mode (also kernel mode or system mode) –execution done on
behalf of operating system.

17
 Mode bit added to computer hardware to indicate the current mode:
› monitor (0)
› or user (1).

 When an interrupt or fault occurs hardware switches to monitor mode.

 Privileged instructions can be issued only in monitor mode.

18
 All I/O instructions are privileged instructions.

 Must ensure that a user program could never gain control of the
computer in monitor mode (I.e., a user program that, as part of its
execution, stores a new address in the interrupt vector).

19
20
 Must provide memory protection at least for the interrupt vector and the interrupt
service routines.
 In order to have memory protection, add two registers that determine the range of
legal addresses a program may access:

› Base register – holds the smallest legal physical memory address.

› Limit register – contains the size of the range

 Memory outside the defined range is protected.


21
22
23
› When executing in monitor mode, the operating system has
unrestricted access to both monitor and user’s memory.

› The load instructions for the base and limit registers are
privileged instructions.

24
 Timer – interrupts computer after specified period to ensure operating
system maintains control.
 Timer is decremented every clock tick.
 When timer reaches the value 0, an interrupt occurs.

 Timer commonly used to implement time sharing.

 Time also used to compute the current time.


 Load-timer is a privileged instruction.
25
 Local Area Networks (LAN)

 Wide Area Networks (WAN)

26
27
28
 Cache:
› Use of high-speed memory to hold recently-accessed data.
› Requires a cache management policy.
 Dual Mode Operation
› Sharing system resources requires operating system to ensure that an incorrect program cannot
cause other programs to execute incorrectly.
 User mode – execution done on behalf of a user.
 Monitor mode (also kernel mode or system mode) –execution done on
behalf of operating system.
› Base register – holds the smallest legal physical memory address.
› Limit register – contains the size of the range
29
 In this lecture we discussed hardware protection, storage
hierarchy , caching, network structures/environments etc.
 CPU protection and memory protection are also
discussed in detail with concept of base and limit register.

30

You might also like