Unit 6 Introduction to Logic

Design with Verilog

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 The purpose of using hardware description languages

(HDLs)
 Describe the functionality of a circuit with texts
 Simulate the functionality with the texts
 Synthesize the texts into circuits
 Logic, timing and power minimizations
 Verify for functionality, timing and fault coverage of the
circuits
 Transform the design between different technologies
 Document the designs
 Serve as a medium for integrating intellectual property (IP)
from a variety of sources

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Verilog primitives and design encapsulation

 Primitives are the most basic functional objects that can
be used to compose a design
 There are 26 predefined functional models of common
combinational logic gates called Primitives:
 N-input: and, nand, or, nor, xor and xnor
 and (OUT, IN1,…,INN); nand (OUT, IN1,…,INN); …

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 or (OUT, IN1,…,INN); nor (OUT, IN1,…,INN); …

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 N-output: buf (OUT1,…, OUTN, IN); 

IN 0 1 X Z
OUT 0 1 X X

 N-output: not (OUT1,…, OUTN, IN);

IN 0 1 X Z
OUT 1 0 X X

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 N-output: buf, not, bufif0, bufif1, notif0, notif1

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Verilog structural module

 A module is declared by writing text describes its
functionality, its ports to/form the environment and its
timing and other attributes of a design
module <module name> ( <list of ports> );
input <width> <input port name>;
output <width> <output port name>;
<variable declarations>
‘;;;;;;
<statements>
endmodule
 A Verilog statement ends with ‘;’, except for endmodule
 A port’s mode may be
 unidirectional (input, output) or
 bidirectional (inout)

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 Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Verilog structural models

 Verilog is case sensitive
 Use nested module instantiations to create a top-down
design hierarchy

module Add_half_0_delay(sum, cout, a, b);  module Add_full_0_delay(sum, cout, a, b, cin); 

　 // declaration of ports 　　　　  　 // declaration of ports 　　　　 
　 input a, b;  　 input a, b, cin; 
   output sum, cout;    output sum, cout;

xor (sum,a,b); wire w1,w2,w3;

and (cout,a,b);
endmodule Add_half_0_delay M1(w1,w2,a,b);
M1
  Add_half_0_delay M2(sum,w3,cin,w1);
M2
or (cout,w2,w3);
endmodule
Instantiation  

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Top-Down design and nested modules

 A vector encloses a contiguous range of bit, e.g. sum[3:0]
 The leftmost index in the bit range is the most significant
bit
 Modeling a 4-bit ripple carry
module Add_rca_4_0_delay(sum, adder
cout, a, b, cin); 
   output[3:0] sum;
output cout;
input[3:0] a, b;
input cin;
wire cin2, cin3, cin4;

Add_full_0_delay M1(sum[0],
M1 cin2, a[0], b[0], cin );
Add_full_0_delay M2(sum[1],
M2 cin3, a[1], b[1], cin2 );
Add_full_0_delay M3(sum[2],
M3 cin4, a[2], b[2], cin3 );
Add_full_0_delay M4(sum[3],
M4 cout, a[3], b[3], cin4 );
endmodule
 

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Top-Down design and nested modules (continued)

 Modeling a 16-bit ripple carry adder
module Add_rca_16_0_delay(sum, cout, a, b, cin); 
   output[15:0] sum;
output cout;
input[15:0] a, b;
input cin;
wire cin4, cin8, cin12;

Add_full_0_delay M1(sum[3:0],
M1 cin4, a[3:0], b[3:0], cin );
Add_full_0_delay M2(sum[7:4],
M2 cin8, a[7:4], b[7:4], cin4 );
Add_full_0_delay M3(sum[11:8],
M3 cin4, a[11:8], b[11:8], cin8 );
Add_full_0_delay M4(sum[15:12],
M4 cout, a[15:12], b[15:12], cin12 );
endmodule
 

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Top-Down design and nested modules (continued)

 Modeling a 2-bit comparator
module compare_2_str(AgtB, AltB, AeqB, A, B); 
   output AgtB, AltB, AeqB;
input[1:0] A, B;
wire[6:0] w;

nor (AgtB, AltB, AeqB);

or (AltB, w[0], w[2]);
not (w[5], A[1]);
not (w[6], A[0]);
and (w[0], w[5], B[1]);
and (w[1], w[6], B[0]);
and (w[2], w[1], w[3]);
xnor (w[3], A[1], B[1]);
xnor (w[4], A[0], B[0]);
and (AeqB, w[3], w[4]);
endmodule
 
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Top-Down design and nested modules (continued)

 Modeling a 4-bit comparator

module compare_4_str(AgtB, AltB, AeqB, A, B); 

   output AgtB, AltB, AeqB;
input[3:0] A, B;
wire w1, w2;

compare_2_str M1(AgtB_M1, AltB_M1, AeqB_M1, A[3:2], B[3:2]); 

compare_2_str M0(AgtB_M0, AltB_M0, AeqB_M0, A[1:0], B[1:0]);  
or (AgtB, AgtB_M1, w1);
and (w1, AeqB_M1, AgtB_M0);
and (AeqB, AeqB_M1, AeqB_M0);
or (AltB, AltB_M1, w0);
xnor (w0, AeqB_M1, AeqB_M0);
endmodule
 

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Logic Test Bench

 Simulating a hall adder with procedural statements
 A single-pass behavior

Module t_Add_half( ); 

　 wire sum, cout;  Procedural assignment: e.g. B=0
   reg a,b;

Add_half_0_delay M1(sum, cout, a, b);

module Add_half_0_delay(sum, cout, a, b); 
initial begin 　 // declaration of ports 　　　　 
#10 a=0; b=0; 　 input a, b; 
#10 b=1;    output sum, cout;
#10 a=1;
#10 b=0; xor (sum,a,b);
end and (cout,a,b);
endmodule endmodule
   
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Verilog structural and behavioral modeling

 Structural modeling connects primitive gates and/or
functional units to create a special functionality just as parts
are connected on a chip or a circuit board
 And, or, xor …
 Truth table
 Designer don’t not perform their gate-level implementation
directly. Instead, they write behavioral models
 Behavioral modeling encourages designers to
 rapidly create a behavioral prototype
 verify its functionality
 Use a synthesis tool to optimize and map the design into a
selected physical technology

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Behavioral modeling provides flexibility to model portions

of a design with different levels of abstraction
 Continuous assignment for combinational logics
 A tri-state functional output 
assign yout = enable ? ~ (x1 & x2)|(x3 & x4 & x5) : 1’bz;
 A nand gate  assign q = b ~& a;
 assign AgtB =A1&(~B1)|A0&(~B1)&(~B0)|A1&A0&(~B0);
 A full adder
 assign sum= a0^a1^a2;
 assign carry=(a0&a1)|(a1&a2)|(a0&a2);
 Propagation delay can be associated with a continuous
assignment
 wire #1 yout = ~(y1|y2);

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Latches and level-sensitive circuits

 Modeling with continuous assignment
 assign q = set ~q qbar;
 assign qbar = rst ~& q;
 Modeling with a more abstract level
 q_out = enable ? data_in : q_out;
 A latch with reset
 q_out = !resetn ? 0 : enable ? data_in : q_out;
 Continuous assignment are limited to modeling level-
sensitive behavior
 How to model edge-sensitive functionality
 Use cyclic behavior of procedure statements

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Cyclic behavior (do not expire)

 Are abstract  do not use hardware to specify signal values
 Are used to model both level-sensitive and edge-sensitive
(synchronous) behavior (e.g. flip-flops)
module df_syn_reset (q, q_bar, data, set, reset, clk); 
   output q, q_bar;
　 input data, set, reset, clk; 
reg q
Continuous statements
assign q_bar = ~q; Always declares a cyclic behavior
always @ (posedge clk) begin //D-FF with synchronous set./reset
if (reset == 0) q <= 0;
else if (set ==0) q <=1; Procedural statements
else q <= data
end
endmodule
 
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 A behavioral model for D-FF with asynchronous set/reset

module df_syn_reset (q, q_bar, data, set, reset, clk); 
   output q, q_bar;
　 input data, set, reset, clk; 
reg q
Edge sensitive event-control expression
assign q_bar = ~q;

always @ (negedge set or negedge reset posedge clk) begin

if (reset == 0) q <= 0;
else if (set ==0) q <=1;
else q <= data
end
endmodule
 

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 A comparison between continuous and procedural

assignments
module compare_2_CA(AltB, AgtB, AeqB, A1, A0, B1, B0); 
　 input A1, A0, B1, B0; 
   output AltB, AgtB, AeqB;
assign AgtB = ({A1, A0} > {B1, B0});
assign AltB = ({A1, A0} < {B1, B0});
assign AeqB = ({A1, A0} == {B1, B0});
endmodule
  module compare_2_RTL(AltB, AgtB, AeqB, A1, A0, B1, B0); 
　 input A1, A0, B1, B0; 
   output AltB, AgtB, AeqB;
reg AltB, AgtB, AeqB;
always@ (A0 or A1 or B0 or B1) begin
AgtB = (A>B);
AltB = (A<B);
AeqB = (A==B); Level sensitive event-control expression
end
endmodule
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Data dependence among sequential procedural statements

module shiftreg_PA(A, E, clk, rst); 
　 input E, clk, rst; 
   output A;
reg A, B, C, D;
always@ (posedge clk or posedge rst) begin
if rst begin A=0, B=0, C=0, D=0; end
else begin
module shiftreg_PA(A, E, clk, rst); 
A = B;
　 input E, clk, rst; 
B = C;
   output A;
C = D;
reg A, B, C, D;
D = E;
always@ (posedge clk or posedge rst) begin
end
if rst begin A=0, B=0, C=0, D=0; end
endmodule
else begin
 
D = E;
Statements execute C = D; A=E
sequentially, but at the B = C;
same time step A = B;
end
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endmodule 20
Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 The statements that follow a procedural assignment are

blocked from executing until the statement with the
procedural assignment completes execution
 blocked assignment
 Concurrent procedural assignments
 Also called non-blocking assignments
 Made with <= module shiftreg_NB(E, A, clk, rst); 
　 input E, clk, rst; 
 Execute concurrently,    output A;
rather sequentially reg A, B, C, D;
always@ (posedge clk or posedge rst) begin
if rst begin A=0, B=0, C=0, D=0; end
else begin
D <= E;
C <= D;
B <= C;
A <= B; end
Department of Communicationendmodule
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 To prevent any interaction between assignments and

eliminates dependences on their relative order
 Modeling logic that includes edge-driven register transfers
 non-blocking assignments
 Modeling combinational logic with
 blocked assignments

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 Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Register transfer level (RTL) v.s. algorithm-based models

 Dataflow models for synchronous machines
module compare_2_RTL(AltB, AgtB, AeqB, A, B); 
　 input[1:0] A, B; 
   output AltB, AgtB, AeqB;
reg AltB, AgtB, AeqB;
always@ (A or B) begin
module compare_2_algo(AltB, AgtB, AeqB, A, B); 
AgtB = (A>B);
　 input A, B; 
AltB = (A<B);
   output AltB, AgtB, AeqB;
AeqB = (A==B);
reg AltB, AgtB, AeqB;
end
always@ (A or B) begin
endmodule
AltB=0; AgtB =0;= AeqB=0;
if (A==B) AeqB =1;
 Algorithm-based
else if (A > B); AgtB =1;
=
modeling else AltB = 1;
end
endmodule

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Comparison between RTL and algorithm modeling

 The assignments in a dataflow (RTL) model execute
concurrently and operate on explicitly declared registers in
the context of a specified architecture
 The statements in an algorithmic model execute
sequentially, without explicit architecture
 Note!!
Not all algorithms can be implemented in hardware

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Behavioral models of Multiplexers

module Mux_4_32 (mux_out, D3, D2, D1, D0, select, enable); 
　 output [31:0] mux_out; 
   input [31:0] D3, D2, D1, D0;
input [1:0] select;
input enable;

reg [31:0] mux_int;

assign mux_out = enable ? Mux_int: 32’bz;

always @ (D3 or D2 or D1 or D0 or select)
case (select)
0: mux_int = D0;
1: mux_int = D1;
2: mux_int = D2;
3: mux_int = D3;
default: mux_int = 32’bx;
endcase
endmodule
 
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Alternative behavioral modeling using if - else

module Mux_4_32 (mux_out, D3, D2, D1, D0, select, enable); 
　 output [31:0] mux_out; 
   input [31:0] D3, D2, D1, D0;
input [1:0] select;
input enable;

reg [31:0] mux_int;

assign mux_out = enable ? Mux_int: 32’bz;

always @ (D3 or D2 or D1 or D0 or select)
if (select == 0) mux_int = D0;
else if (select == 1) mux_int = D1;
else if (select == 2) mux_int = D2;
else if (select == 3) mux_int = D3;
else mux_int = 32’bx;
endmodule
 

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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Behavioral models of Encoders

module encoder (code, data); 
　 output [2:0] code; 
   input [7:0] data;

reg [2:0] code;

always @ (data)
if (data == 8’b00000001) code = 0;
else if (data == 8’b00000010) code = 1;
else if (data == 8’b00000100) code = 2;
else if (data == 8’b00001000) code = 3;
else if (data == 8’b00010000) code = 4;
else if (data == 8’b00100000) code = 5;
else if (data == 8’b01000000) code = 6;
else if (data == 8’b10000000) code = 7;
else code = 3’bx;
endmodule
 
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Alternative behavioral modeling of Encoders

module encoder (code, data); 
　 output [2:0] code; 
   input [7:0] data;

reg [2:0] code;

always @ (data)
case (data)
8’b00000001 : code = 0;
8’b00000010 : code = 1;
8’b00000100 : code = 2;
8’b00001000 : code = 3;
8’b00010000 : code = 4;
8’b00100000 : code = 5;
8’b01000000 : code = 6;
8’b10000000 : code = 7;
default : code = 3’bx;
endcase
endmodule
 
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Behavioral models of Priority Encoders

module priority_encoder (code, valid_data, data); 
　 output [2:0] code; 
output valid_data;
   input [7:0] data;
reg [2:0] code;
assign valid_data = |data;
always @ (data)
casex (data)
8’b1xxxxxxx : code = 7;
8’b01xxxxxx : code = 6;
8’b001xxxxx : code = 5;
8’b0001xxxx : code = 4;
8’b00001xxx : code = 3;
8’b000001xx : code = 2;
8’b0000001x : code = 1;
8’b00000001 : code = 0;
default : code = 3’bx;
endcase
endmodule
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Digital CAS Unit 3 Introduction to Verilog Sau-Hsuan Wu

 Behavioral models of Decoders

module decoder (data, code); 
　 output [7:0] data; 
   input [2:0] code;

reg [7:0] data;

always @ (code)
case (code)
0: data = 8’b00000001;
1: data = 8’b00000010;
2: data = 8’b00000100;
3: data = 8’b00001000;
4: data = 8’b00010000;
5: data = 8’b00100000;
6: data = 8’b01000000;
7: data = 8’b10000000;
default : data = 8’bx;
endcase
endmodule
 
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 Behavioral models of Counters

module up_down_counter (Count, Data_in, Load, Count_up, Count_on, CLK, RstN); 

　 output [2:0] Count; 

   input Load, Count_up, Count_on, CLK, RstN;

   input [2:0] Data_in;

reg [2:0] Count;

always @ (posedge CLK or negedge RstN)
if (RstN == 0) Count = 3’b0;
else if (Load == 1) Count = Data_in;
else if (Count_on == 1) begin
if (Count_up == 1) Count = Count + 1;
else Count = Count - 1;

end
endmodule
 
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 Behavioral models of Shift Registers

module shift_reg4 (Data_out, Data_in, CLK, RstN); 

　 output Data_out; 

   input Data_in, CLK, RstN;

reg [3:0] data_reg;

assign Data_out = data_reg[0];

always @ (posedge CLK or negedge RstN) begin
if (RstN == 0) data_reg <=
< 4’b0;
else data_reg <=
< {Data_in, data_reg[3:1]};
end
endmodule
 

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