1

Computer System Architecture

(THIRD EDITION)

M. Morris Mano

PRENTICE HALL
Computer System Architecture Chap. 1 Digital Logic Circuits Ref: bazi.pe.kr
 최초의 컴퓨터 ? 2

 ENIAC (1946)

Computer System Architecture Chap. 1 Digital Logic Circuits

 Von Neumann Architecture 3

 John von Neumann & EDVAC

Computer System Architecture Chap. 1 Digital Logic Circuits

 Quiz 4

Computer System Architecture Chap. 1 Digital Logic Circuits

 5

 Alan Turing (1912-1954)

Computer System Architecture Chap. 1 Digital Logic Circuits

 AI Assistant 6

 AMAZON – Alexa, Google Assistant, SK-NUGU (Aria)


 https://www.youtube.com/watch?v=xfItjWHJ-Gk

 https://www.youtube.com/watch?v=CBeDsJie6qk

 https://www.youtube.com/watch?v=FDPg7fv24UQ

Computer System Architecture Chap. 1 Digital Logic Circuits

 Class Overview 7

 Contents
 Basic Computer Hardware Architecture
 CPU, Memory, I/O System Design
 Advanced Topics: Pipeline, Multiprocessor
 Related Subject
 Digital Logic ( 논리설계 ), Discrete Mathematics ( 이산수학 )
 Chapter Outline
 Ch. 1 ~ Ch. 4: Digital Computer Hardware Architecture
 Ch. 5 ~ Ch. 7: Basic Computer Design
 Ch. 8 ~ Ch. 10: CPU Architecture and Pipeline Processing
 Ch. 11 ~ Ch. 12: I/O and Memory Architecture
 Ch. 13: Multiprocessor
 Homework
 Solve the selected number of problems
 Report of Survey for given theme
 Reference
 Morris Mano, Computer Systems Architecture, Prentice-Hall, 3rd Ed.
 John Hennessy, David Patterson, Computer Architecture: a Quantitative approach, Morgan
Kaufmann. 3rd Ed.

Computer System Architecture Chap. 1 Digital Logic Circuits

 A Simple Picture 8

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-1 Digital Computers 9

 Digital – A limited number of discrete value

 Bit – A Binary Digit Application
ApplicationS/W
S/W
 Program – A Sequence of instructions

 Computer = H/W + S/W API

API
 Program(S/W) Operating
 A sequence of instruction
OperatingSystem
System
 S/W = Program + Data
 The data that are manipulated by the
program constitute the data base ROM BIOS
ROM BIOS
 Application S/W
 DB, word processor, Spread Sheet, game Computer
ComputerH/W
H/W
 System S/W
 OS, Firmware, Compiler, Device Driver

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-1 Digital Computers 10

 Computer Hardware
 CPU
 Memory
 Program Memory(ROM)
Memory
Memory
 Data Memory(RAM)

 I/O Device
 Input Device: Keyboard, Mouse,
Scanner
 Output Device: Printer, Plotter, CPU
CPU
Display
 Storage Device(I/O): FDD, HDD,
MOD
Input Output
Input
Device
Interface
Interface
Output
Device
Device Device

Figure 1-1 Block Diagram of a digital Computer

Computer System Architecture Chap. 1 Digital Logic Circuits

 Example: Recipe 11

Program code

: Set of instructions
UI/UX

Data

Ref) http://www.eatsamazing.co.uk/recipes-tutorials/cooking-with-small-child-homemade-burgers

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-1 Digital Computers 12

 What is “Computer Architecture”?

- Hennessy and Patterson, Computer Organization and Design(1990)
 Computer Architecture
 Instruction Set Architecture (ISA)
 Machine Organization

 “ISA”?
 Instructions
 Addressing modes
 Instruction and data formats
 Register
 “Machine Organization”?
 CPU(Control, Data path), Memory, Input, Output

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-2 Logic Gates 13

 ADC(Analog to Digital Conversion)

 Signal Physical Quantity Binary Information
0 : 0.5
V, A, F, 거리 Discrete Value
 Gate
1: 3
 The manipulation of binary information is done by logic circuit called
“gate”.
 Fig. 1-2 Digital Logic Gates
 AND, OR, INVERTER, BUFFER, NAND, NOR, XOR, XNOR

 George Boole
 Born: 2 Nov 1815 in Lincoln,
Lincolnshire, England
 Died: 8 Dec 1864 in Ballintemple,
County Cork, Ireland

Computer System Architecture Chap. 1 Digital Logic Circuits

 Boole Logic - Example 14

 What is it?
 Input, Output 이 이진변수 (binary variable) 로 구성된 논리
회로
 우주회 ( 雨酒會 )
 비가 오면  술 먹는다
 비가 안 오면  술 안 먹는다 A

 비가 온다 : A = 1, 비가 안 온다 : A = 0
 술 먹는다 : X = 1, 술 안 먹는다 : X = 0

 If (A == 1), Then X = 1; Else, X = 0;

Computer System Architecture Chap. 1 Digital Logic Circuits

 Boole Logic - Example 15

http://nogwon.blogspot.kr/2013/10/blog-post_2036.html

Computer System Architecture Chap. 1 Digital Logic Circuits

 Boole Logic - Example 16

 비 (A) 가 오고 친구 (B) 가 있으면  술 (X) 먹는다

 If (A==1)&&(B==1), Then X = 1; Else, X = 0;

A
X
B

 비 (A) 가 오고 친구 (B) 가 있고 돈 (C) 이 있으면  술 (X) 먹는다

 If (A==1)&&(B==1)&&(C==1), Then X = 1; Else, X = 0;

A
B X
C
Computer System Architecture Chap. 1 Digital Logic Circuits
 1-2 Logic Gates 17

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-2 Logic Gates 18

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-3 Boolean Algebra 19

 Boolean Algebra
 Deals with binary variable(A, B, x, y: T/F or 1/0) + logic
operation(AND, OR, NOT…)
 Boolean Function: variable + operation
 F(x, y, z) = x + y’z

 Truth Table: Fig. 1-3(a)  Logic Diagram: Fig. 1-3(b)

Relationship between a function Algebraic Expression
and variable Logic Diagram(gates 로 표현 )

x y z F
0 0 0 0
0 0 1 1 x

0 1 0 0 y
2n Combination F
0 1 1 0
Variable n = 3 1 0 0 1 z
1 0 1 1
1 1 0 1
1 1 1 1

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-3 Boolean Algebra 20

 Purpose of Boolean Algebra

 To facilitate the analysis and design of digital circuit
 Convenient Tools
 Truth table : relationship between binary variables
 Logic diagram : input-output relationship
 Find simpler circuits for the same function
 Boolean Algebra Rule : Tab. 1-1

- Operation with 0 and 1: x + 0 = x , x + 1 = 1 , x • 1 = x , x • 0 = 0

- Idempotent Law: x + x =x , x • x = x
- Complementary Law: x + x' = 1 , x • x' = 0
- Commutative Law: x + y = y + x , x • y = y • x
- Associative Law: x + (y + z) = (x + y) + z , x • ( y • z) = (x • y) • z
- Distributive Law: x • ( y+ x) = (x • y) + (x • z) , x + (y • z) = (x + y) • (x + z)
- DeMorgan's Law: (x + y)' = x' • y’ , (x • y )’ = x’ + y’
( A  B ) c  Ac  B c
General Form: (x1 + x2 + x3 + … xn)' = x1' • x2' • x3' • … xn’
(x1 • x2 • x3 • … xn) ' = x1' + x2' + x3' + … xn’
Computer System Architecture Chap. 1 Digital Logic Circuits
 1-3 Boolean Algebra 21

 [ 예제 ]  [ 예제 ] Fig. 1-6(a)
 F= AB’ + C’D + AB’ + C’D
 F= ABC + ABC’ + A’C
= x + x (let x= AB’ + C’D)
= AB(C + C’) + A’C Fig. 1-6(b)
=x
= AB + A’C
= AB’ + C’D
1 inverter, 1 AND gate 감소
 Fig. 1-4 2 graphic symbols for NOR gate
x x
y (x+y+z)’ y x’ y’z’
z z

(a) OR-invert (b) invert-OR

 Fig. 1-5 2 graphic symbols for NAND gate
x x
y (xyz)’ y (x’+y’+z’)
z z

(a) NAND-invert (b) invert-NAND

Computer System Architecture Chap. 1 Digital Logic Circuits
 1-3 Boolean Algebra 22

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-4 Map Simplification 23

 Karnaugh Map(K-Map)
 Map method for simplifying Boolean expressions
 Minterm / Maxterm
 Minterm : n variables product ( x=1, x’=0)
 Maxterm : n variables sum (x=0, x’=1)
 2 variables example
x y Minterm Maxterm
0 0 x'y' m0 x +y M0
0 1 x'y m1 x + y' M1
1 0 x y' m2 x'+ y M2
1 1 x y m3 x'+ y' M3

 F = x’y + xy m0 + m1 + m2 + m 3 M0  M1  M2  M3
m1 m3
 (1,3) ( m1 + m3 )

  (0,2) (Complement = M0  M2 )

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-4 Map Simplification 24

 Map
 2 variables
 3 variables  4 variables
C
B B

0 1 0 1 3 2
0 1 3 2
A 2 3 A 4 5 7 6 4 5 7 6
B
12 13 15 14
C A
 5 variables C
8 9 11 10
D
0 1 3 2 6 7 5 4
8 9 11 10 14 15 13 12
B
A
24 25 27 26 30 31 29 28
16 17 19 18 22 23 21 20
E D F

Fig 1-7 Maps for two-, three-, four-, and five-variable functions

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-4 Map Simplification 25

 [ 예제 ] F= x + y’z

(1) Truth Table (2) F ( x, y , z )  (1,4,5,6,7)

x y z F Minterm (3) Karnaugh Map
y
0 0 0 0 m0
0 0 1 1 m1 0 1 3 2
0 1 0 0 m2
4 5 7 6
0 1 1 0 m3 x

1 0 0 1 m4
z
1 0 1 1 m5
1 1 0 1 m6
1 1 1 1 m7 F= x + y’z

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-4 Map Simplification 26

 Adjacent Square
 Number of square = 2n (2, 4, 8, ….)
 The squares at the extreme ends of the 0 1 3 2

same horizontal row are to be 4 5 7 6

considered adjacent
0 1 3 2

 The same applies to the top and 4 5 7 6

bottom squares of a column 12 13 15 14

8 9 11 10

 The four corner squares of a map must 0 1 3 2

be considered to be adjacent 0 1 3 2
4 5 7 6
4 5 7 6
12 13 15 14

 Groups of combined adjacent squares 8 9 11 10

may share one or more squares with 0 1 3 2

one or more group 4 5 7 6

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-4 Map Simplification 27

 [ 예제 ] B
F ( A, B, C )  (3,4,6,7)
 F=AC’ + BC 0 1 3 2
A 4 5 7 6

C B
 [ 예제 ] F ( A, B, C )  (0,2,4,5,6)
0 1 3 2
 F=C’ + AB’ A 4 5 7 6

C C
 [ 예제 ] F ( A, B, C , D )  (0,1,2,6,8,9,10)
0 1 3 2
 F=B’C’ + B’D’ + A’CD’
4 5 7 6 B

A
12 13 15 14
 Product-of-Sums Simplification 8 9 11 10
F ( A, B, C , D )  (0,1,2,5,8,9,10) D C

F=B’D’ + B’C’ + A’C’D Sum of product 0 1 3 2

4 5 7 6 B
F’=AB + CD + BD’(square marked 0’s) A
12 13 15 14
F’’(F)=(A’ + B’)(C’ + D’)(B’ + D) 8 9 11 10
Product of Sum
D
Computer System Architecture Chap. 1 Digital Logic Circuits
 1-4 Map Simplification 28

 NAND Implementation
 Sum of Product : F=B’D’ + B’C’ + A’C’D

B’
D’

C’

A’
D
 NOR Implementation
 Product of Sum : F=(A’ + B’)(C’ + D’)(B’ + D)

A’
B’
C’
D’

D’ B
 Don’t care conditions 0 1 3 2

 F(A,B,C)=(0, 2, 6), d(A,B,C)= (1, 3, 5) 1 X X 1

4 5 7 6

 F=A’ + BC’= (0, 1, 2, 3, 6) A X

C

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-5 Combinational Circuits 29

 Combinational Circuits
 A connected arrangement of logic gates with a set of inputs and outputs
 Fig. 1-15 Block diagram of a combinational circuit

i0 f0
i1 Combinational f1

...

...
Circuits
(Logic Gates)
in fm
 Analysis
 Logic circuits diagram Boolean function or Truth table
 Design(Analysis 의 반대 )
Experience
 1. The Problem is stated
 2. I/O variables are assigned
 3. Truth table(I/O relation)
 4. Simplified Boolean Function(Map 과 Boolean 대수 이용 )
 5. Logic circuit diagram

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-5 Combinational Circuits 30

 Design Example : Half Adder

 1. Half adder is a combinational circuits that forms the arithmetic sume
of two input bit
 2. 2 Input(x, y), 2 Output(S: sum, C: carry)
 3. Truth Table
 4. Simplification

C= xy S= x’y + xy’
=x  y
 5. Logic circuit diagram  6. Block diagram

X S
H.A

y C

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-5 Combinational Circuits 31

 Design Example : Full Adder

 1. Full adder is a combinational circuits that forms the arithmetic sume
of three input bit(Carry considered)
 2. 3 Input(x, y, z), 2 Output(S: sum, C: carry)
 3. Truth Table
 4. Simplification
y y
Input Output
x y z C S
0 0 0 0 0 0 1 3 2 0 1 3 2
0 0 1 0 1
x 4 5 7 6 x 4 5 7 6
0 1 0 0 1
0 1 1 1 0 z
z
1 0 0 0 1 S=xy’z’ + x’y’z + xyz + x’yz’
C= xy’z + x’yz + xy
1 0 1 1 0
1 1 0 1 0 =z(xy’ + x’y) + xy = z’(xy’ + x’y) + z(x’y’ + xy)
1 1 1 1 1 =z(x  y) + xy = z’(x  y) + z(x  y)’
=a’b + ab’ (let a=z, b=x  y)
 5. Logic circuit diagram =x  y  z
x
y (x y)’=(xy’+x’y)’
c
=(x’+y)(x+y’)
z =x’x+x’y’+xy+yy’
=x’y’+xy
s

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-5 Combinational Circuits 32

X
F. A S

Y
C

Fig 1-18. Block diagram

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-6 Flip-Flops 33
Combinational Circuit = Gate
Sequential Circuit = Gate + F/F
 Flip-Flop
 The storage elements employed in clocked sequential circuit
 A binary cell capable of storing one bit of information
 SR(Set/Reset) F/F
 D(Data) F/F
SET
SET S R Q(t+1) D Q
S Q D Q(t+1)
0 0 Q(t) no change
0 0 clear to 0
0 1 0 clear to 0
1 1 set to 1
1 0 1 set to 1 Q
R C LR
Q 1 1 ? Indeterminate
C LR

 “no change” condition 이 없다 : Q(t+1)=D

 해결방법 : 1) Disable Clock

2) Feedback output into input

 JK(Jack/King) F/F  T(Toggle) F/F
SET J K Q(t+1)
J Q SET
0 0 Q(t) no change T Q T Q(t+1)
0 1 0 clear to 0 0 Q(t) no change
1 0 1 set to 1 1 Q'(t) Complement
K Q 1 1 Q(t)' Complement
C LR
C LR
Q
 JK F/F is a refinement of the SR F/F
 T=1(J=K=1), T=0(J=K=0) 이면 JK F/F
 The indeterminate condition of the SR
type is defined in complement  수식 표현 : Q(t+1)= Q(t)  T

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-6 Flip-Flops 34

 SR(Set/Reset) F/F  D(Data) F/F

SET SET
S S Q
Q’ S S Q
D

CP
R C LR
Q R C LR
Q

Q R
R

 JK(Jack/King) F/F  T(Toggle) F/F

SET SET
J S Q T J Q

CP
R C LR
Q K C LR
Q

E
Computer System Architecture Chap. 1 Digital Logic Circuits
 1-6 Flip-Flops 35

Positive clock transition

 Edge-Triggered F/F
 State Change : Clock Pulse
 Rising Edge(positive-edge transition)
 Falling Edge(negative-edge transition)

 Setup time(20ns) ts th
 minimum time that D input must remain at constant value before the transition.
 Hold time(5ns)
 minimum time that D input must not change after the positive transition.

 Propagation delay(max 50ns)

 time between the clock input and the response in Q
 일반 논리 gate 에서는 2-20 ns 이며 setup 및 hold time 은 F/F 에서만 정의되며 일반 논리
gate 에서는 정의되지 않음 .
 Master-Slave F/F
 2 개의 F/F 을 사용 (Slave 와 Master F/F) 하며 negative-edge transition 사용
 위와 같이 사용하는 이유 : Race 현상을 방지

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-6 Flip-Flops 36

 Master – Slave D(Data) F/F

D D D Q
Master Slave

C C

a. 논리도 b. 파형도

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-6 Flip-Flops 37

 Race 현상
 조건 - Setup time > Propagation delay
 증상 - 0 과 1 을 반복하다가 Unstable 한 상태가 된다
 해결책 - Edge triggered F/F 또는 Master/Slave F/F 사용
 예제
 7470 : J-K Edge triggered F/F
 7471 : J-K Master/Slave F/F

 Excitation Table
 Required input combinations for a given change of state
 Present State 와 Next State 로 표현

SR F/F JK F/F D F/F T F/F

Q(t) Q(t+1) S R Q(t) Q(t+1) J K Q(t) Q(t+1) D Q(t) Q(t+1) T
0 0 0 X 0 0 0 X 0 0 0 0 0 0
0 1 1 0 0 1 1 X 0 1 1 0 1 1
1 0 0 1 1 0 X 1 1 0 0 1 0 1
1 1 X 1 1 1 X 0 1 1 1 1 1 0

1 : Set to 1 1 : Clear to 0
Don’t Care 0 : Complement 0 : No change

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-7 Sequential Circuits 38

 A sequential circuit is an interconnection of F/F and Gate

 Clocked synchronous sequential circuit
Combinational Circuit = Gate
Sequential Circuit = Gate + F/F
Input Combinational
Circuit Output
Flip-Flops

Clock

 Flip-Flop Input Equation

 Boolean expression for F/F input DA SET

x D Q A
 Input Equation 예제
 DA = Ax + Bx, DB = A’x C LR
Q A’

 Output Equation
 y = Ax’ + Bx’
DB SET
D Q B
 Fig. 1-25 Example of a sequential
Clock
circuit C LR
Q B’

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-7 Sequential Circuits 39

 State Table  State Diagram

 Present state, input, next state, output 표현  Graphical representation of state
Input Equ. = Next State table
 Circle(state), Line(transition),
Present State Input Input Equ. Next State Output
A B x Ax Bx DA DB A B y I/O(input/output)
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 1 0 0 /0 1 /0
0 1 0 0 0 0 0 0 0 1
0 1 1 0 1 1 1 1 1 0 00 10
1 0 0 0 0 0 0 0 0 1 0 /1
1 0 1 1 0 1 0 1 0 0
1 1 0 0 0 0 0 0 0 1 JK F/F
Q(t) Q(t+1) J K
1 1 1 1 1 1 0 1 0 0 0 /1 1 /0
0 0 0 X 0 /1 1 /0
0 1 1 X
 Design Example: Binary Counter 1
1
0
1
X
X
1
0

x=0 0 /0 0 x=0 Next State =

01 11
Output 1 /0
00 10
 x=1: 00, 01, 10, 11, x=1  Excitation Table(2 bit counter = 2 F/F)
00, 01, …..
Present State Input Next State u F/F Input
x=0: no change A B x A B JA KA JB KB
x = 1 1 /0 1 x=1
0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 x 1 x
 State Diagram:
0 1 0 0 1 0 x x 0
4 state(00, 01, 10, 11) 01 11
0 1 1 1 0 1 x x 1
1 0 0 1 0 x 0 0 x
x=1
1 0 1 1 1 x 0 1 x
1 1 0 1 1 x 0 x 0
x=0 x=0
1 1 1 0 0 x 1 x 1

Computer System Architecture Chap. 1 Digital Logic Circuits

 1-7 Sequential Circuits 40

 Map for simplification  Logic Diagram

 Input variable: A, B, x
B B
SET

KA x J Q A
JA 0 1 3 2 0 1 3 2
1 X X X X
4 5 7 6 4 5 7 6 K Q
A X X X X A 1 CLR

x x
JA=Bx KA=Bx
B B
SET

JB 0 1 3 2 KB 0 1 3 2
J Q B
1 X X X X 1
4 5 7 6 4 5 7 6
A 1 X X A X X 1 K CLR
Q
x x
C lo c k
JB=x KA=x
 Sequential Circuit Design Procedure 1. The Problem is stated
2. I/O variables are assigned
 1-5 절 참고 (Combinational Circuit Design) 3. Truth table(I/O relation)
 Sequential Circuit 은 절차 3 에서 State 4. Simplified Boolean Function
5. Logic circuit diagram
diagram 및 State table 이용
 F/F 수 : 2m+n (m - State 수 , n - Input 수 )

Computer System Architecture Chap. 1 Digital Logic Circuits