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Chapter3 3

The document discusses implementing logic gates using NAND and XOR. It covers converting between AND/OR and NAND representations using DeMorgan's Law. Multi-level logic can be converted to NAND gates by introducing bubbles to match inputs. XOR gates provide efficient implementations for parity generation and checking, and the XOR function can also be realized with AND and OR gates.

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deepti shrimankar
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21 views20 pages

Chapter3 3

The document discusses implementing logic gates using NAND and XOR. It covers converting between AND/OR and NAND representations using DeMorgan's Law. Multi-level logic can be converted to NAND gates by introducing bubbles to match inputs. XOR gates provide efficient implementations for parity generation and checking, and the XOR function can also be realized with AND and OR gates.

Uploaded by

deepti shrimankar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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ENGIN 112

Intro to Electrical and Computer


Engineering
Lecture 11

NAND and XOR Implementations

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Overvie
w
° Developing NAND circuits from K-maps
° Two-level implementations
• Convert from AND/OR to NAND (again!)

° Multi-level NAND implementations


• Convert from a network of AND/ORs

° Exclusive OR
• Comparison with SOP

° Parity checking and detecting circuitry


• Efficient with XOR gates!

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


NA
ND-
NA
DeMorgan’s
ND Law:
& (a + b)’ = a’ b’ (a b)’ = a’ + b’
NO
R- a + b = (a’ b’)’ (a b) = (a’ + b’)’
NO
R
Net = =
wor
ks = =

push bubbles or introduce in pairs or remove pairs.

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


NAND-NAND Networks

° Mapping from AND/OR to NAND/NAND

a) b)
a
b
c
d

c) d)

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Imp
lem
°ent
Sum-of-products
atio
ns • AND gates to form product terms
(minterms)
of • OR gate to form sum
Two
-
leve
l
°Log
Product-of-sums
ic • OR gates to form sum terms
(maxterms)
• AND gates to form product

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Two
-
°leve
lReplace minterm AND gates with NAND gates
°Log
Place compensating inversion at inputs of OR gate
ic
usi
ng
NA
ND
Gat
es

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Two
-
°leve
lOR gate with inverted inputs is a NAND gate
• de Morgan's: A' + B' = (A • B)'
Log
°ic
Two-level NAND-NAND network
usi• Inverted inputs are not counted
ng • In a typical circuit, inversion is done once and signal distributed
NA
ND
Gat
es
(co
nt’d
)

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Con
ver
°sio
nConvert from networks of ANDs and ORs to
networks of NANDs and NORs
Bet•
Introduce appropriate inversions ("bubbles")
wee
°nEach introduced "bubble" must be matched by a
corresponding "bubble"
For
ms• Conservation of inversions
• Do not alter logic function

° Example: AND/OR to NAND/NAND

A A
NAND
B B
Z NAND Z
C C
NAND
D D

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Con
ver
°sio
nExample: verify equivalence of two forms
Bet
wee
An A
For NAND
B B
ms Z NAND Z
C(co C
NAND
Dnt’d D
)

Z = [ (A • B)' • (C • D)' ]'


= [ (A' + B') • (C' + D') ]'
= [ (A' + B')' + (C' + D')' ]
= (A • B) + (C • D) 

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Con
ver
°sio
nStart
to with SOP (Sum of Products)
NA• circle 1s in K-maps
°ND
Find network of OR and AND gates
Gat
es

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Mul
ti-
° x =leve
ADF + AEF + BDF + BEF + CDF + CEF + G
l• Reduced sum-of-products form – already simplified
Log
• 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)
ic
• 25 wires (19 literals plus 6 internal wires)
° x = (A + B + C) (D + E) F + G
• Factored form – not written as two-level S-o-P
• 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate
• 10 wires (7 literals plus 3 internal wires)

A
B
C
X
D
E
F
G

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Conversion of Multi-level Logic to NAND
° FGates
= A (B + C D) + B C'
Level 1 Level 2 Level 3 Level 4

C
D
original F
B
AND-OR A
network
B
C’

C
D
introduction and F
B
conservation of
A
bubbles
B
C’

C
redrawn in terms D
F
of conventional B’
NAND gates A
B
C’

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Con
ver
°sio
nExample
Bet
A A
(a) wee
B B (b)
F F
n C X C X
D D
For
Add double bubbles at inputs
msOriginal circuit
A
A X

(c) B F
C (d)
X’ B F
D’ C X’
D’

Distribute bubbles
Insert inverters to fix mismatches
some mismatches

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Exclusive-OR and Exclusive-NOR
Circuits
Exclusive-OR (XOR) produces a HIGH output whenever the two
inputs are at opposite levels.

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Exclusive-NOR Circuits

Exclusive-NOR (XNOR) :
Exclusive-NOR (XNOR) produces a HIGH output whenever the two
inputs are at the same level.

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Exclusive-NOR Circuits
XNOR gate may be used to simplify circuit implementation.

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


XOR
Function
° XOR function can also be implemented with
AND/OR gates (also NANDs).

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


XOR
Function
° Even function – even number of inputs are 1.
° Odd function – odd number of inputs are 1.

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Parity Generation and
Checking
FIGURE 4-25 XOR gates used to implement the parity generator and the parity
checker for an even-parity system.

ENGIN112 L11: NAND and XOR Implementation September 26, 2003


Summary

° Follow rules to convert between AND/OR


representation and symbols
° Conversions are based on DeMorgan’s Law
° NOR gate implementations are also possible
° XORs provide straightforward implementation for
some functions
° Used for parity generation and checking
• XOR circuits could also be implemented using AND/Ors

° Next time: Hazards

ENGIN112 L11: NAND and XOR Implementation September 26, 2003

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