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    System-On-Chip (Soc) Testing

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    Akhil
    This document provides an overview of system-on-chip (SoC) testing and the IEEE 1500 standard for embedded core testing. It defines what an SoC and core are, and discusses new testing issues for SoCs related to core-based design. The IEEE 1500 standard addresses these issues through a generic test access architecture using wrappers, instructions, and a core test language to integrate core tests into the SoC test. The standard supports two compliance levels and provides serial and parallel test access mechanisms.

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    System-On-Chip (Soc) Testing

    Uploaded by

    Akhil
    79 views18 pages
    This document provides an overview of system-on-chip (SoC) testing and the IEEE 1500 standard for embedded core testing. It defines what an SoC and core are, and discusses new testing issues for SoCs related to core-based design. The IEEE 1500 standard addresses these issues through a generic test access architecture using wrappers, instructions, and a core test language to integrate core tests into the SoC test. The standard supports two compliance levels and provides serial and parallel test access mechanisms.

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    soc testing document pdf

    Original Title

    10-SoC-P1500-Overview

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    This document provides an overview of system-on-chip (SoC) testing and the IEEE 1500 standard for embedded core testing. It defines what an SoC and core are, and discusses new testing issues for SoCs related to core-based design. The IEEE 1500 standard addresses these issues through a generic test access architecture using wrappers, instructions, and a core test language to integrate core tests into the SoC test. The standard supports two compliance levels and provides serial and parallel test access mechanisms.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    79 views18 pages

    System-On-Chip (Soc) Testing

    Uploaded by

    Akhil
    This document provides an overview of system-on-chip (SoC) testing and the IEEE 1500 standard for embedded core testing. It defines what an SoC and core are, and discusses new testing issues for SoCs related to core-based design. The IEEE 1500 standard addresses these issues through a generic test access architecture using wrappers, instructions, and a core test language to integrate core tests into the SoC test. The standard supports two compliance levels and provides serial and parallel test access mechanisms.

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    © All Rights Reserved
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    of 18

    System-on-Chip (SoC) Testing

    An Introduction and Overview of IEEE


    1500 Standard Testability Method for
    Embedded Core-based ICs

    1
    What is a SoC?
    Technological advances allow electronic systems that
    earlier occupied one or more boards onto a single IC.
    The attending advantages are:
    Higher performance
    Lower Power consumption
    Smaller volume and weight
    Typically, heterogeneous, containing a mix of:
    Digital logic
    Memories of different formats and types
    Analog circuits
    Embedded cores

    2
    What is a core?
    Large, reusable building blocks
    Reuse speeds up design, brings in external expertise.
    Typical core functions:
    CPUs and DSPs
    Serial interfaces
    Modules for interconnect standards, e.g. PC, USB, IEEE 1394
    (Firewire), and for graphics computation, e.g. MPEG and
    JPEG
    Memories
    Core Types:
    Soft (RTL code)
    Firm (netlist)
    hard (layout)

    3
    Core Providers vs. Core Users
    Cores have changed the nature of
    components used in system design:
    In traditional system-on-board design
    provided components were ICs, designed,
    manufactured, and tested by the provider.
    Users could assume components to be
    fault-free and needed to test only
    interconnect between the components.
    In SoC, components are cores (soft, firm,
    or hard) that are not yet manufactured or
    tested for defects.

    4
    New Testing Issues in SoCs
    Core user responsible for manufacturing and
    testing the SoC
    However, this is not possible without the
    assistance of core provider because core
    design is hidden for IP reasons.
    Typically, core provider assists by delivering
    pre-defined tests with the core.
    The problem that faced the SoC designer was
    how to apply these tests at the core
    boundaries.

    5
    IEEE 1500 Standard for
    Embedded Core Test*
    Stated Purpose: Reduce test cost through improved
    automation, promote good design-for-test (DFT)
    technique, and improve test quality through
    improved access.
    Scalable standard architecture for test reuse and
    integration for embedded cores and associated
    circuitry.
    Only defined for digital circuitry.
    Has serial and parallel test-access mechanisms
    (TAMs) and an instruction set for testing cores, SoC
    interconnect, and circuitry.
    Provides features to isolate and protect cores

    •http://grouper.ieee.org/groups/1500/index.html. See also, E. J. Marinissen et al.,


    Journal of Electronic Testing: Theory and Applications (JETTA), 18, 365-383, 2002. 6
    Generic Test Access Architecture
    Architecture
    components
    Source
    Sink
    TAMs
    Wrapper
    Source/sink
    can be external
    or internal to
    the chip.

    7
    Overview of Wrapper Architecture

    8
    Wrapper Instructions

    9
    Timing: WIR shift, then WIR Update

    10
    Wrapper Boundary Cells

    For Core Input For Core Output

    11
    Wrapper Serial Bypass Example

    12
    Wrapper External Test Mode

    13
    Core Test Language (CTL)
    Purpose: Support all information the core provider needs
    to give for embedding the core in a SoC.
    Requirement: Patterns, which contain bulk of the test data,
    are reusable without any modification.

    CTL Components

    14
    SoC Test Challenges
    Core Test
    Providing DfT inside cores and test patterns to linked
    by SoC designer to chip-level test patterns sources
    and sinks that may be on-chip (BIST) or off-chip
    (ATE)
    Core Test Access: Problems relate to deep
    embedding of cores and their large I/O pins
    compared to chip I/O pins. Sophisticated TAMs
    provide the solution.
    SoC Level Test: How to integrate individual core
    tests and tests for interconnect? The solution
    take the form of test scheduling strategies.

    15
    Two Compliance Levels
    1. Unwrapped Cores: Bare core - no
    wrapper - but must have a CTL
    program for core test at the bare-core
    level, which can be used to design a
    “1500-wrapped” core.
    2. Wrapped Cores: IEEE 1500 wrapper +
    CTL program.

    16
    Example Core and Wrapper

    17
    Instruction Decoding for Serial
    and Parallel Tests

    18

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