Designing Combinational

Logic Circuits
Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f (In, Previous In)

Output = f ( In )

2
Static Complementary
V
CMOS
DD

In1
PMOS only
In2 PUN

…
InN
F(In1,In2,…InN)
In1
In2 PDN
…
NMOS only
InN

PUN and PDN are dual logic networks

3
 Few Important Observations for Static
CMOS design
•Transistor can be thought of as a switch controlled by its gate voltage
•The PDN is constructed using NMOS devices while the PUN is constructed from
PMOS. Primary reason behind this is that NMOS produces very strong zeros and
PMOS produces very strong one. (s5)
•The set of rules can be derived to construct logic functions. (s6)
NMOS transistors connected in series represent an AND function
NMOS transistors connected in parallel correspond to an OR function
•PUN and PDN of CMOS structure are dual networks. (s8)
•The complementary gate is naturally inverting.
•The number of transistor required to implement an N-input logic gate is 2N.(s9)
 ThresholdV Drops
DD VDD
PUN
S D
VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S D

Back
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NMOS Transistors
in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y=X if AandB

X B Y=Xif AORB
Y

NMOSTransistors pass a“strong”0but a“weak”1

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PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y= X if AANDB =A+ B

X B Y= Xif AORB= AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

Back 7
Complementary CMOS Logic Style

Back
8
Example Gate: NAND

9
Example Gate: NOR

10
Complex CMOS Gate
B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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 Constructing a Complex Gate VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D
F

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

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 CMOS Properties
• Full rail-to-rail swing; high noise margins
• Logic levels not dependent upon the relative device sizes; ratioless
• Always a path to Vdd or Gnd in steady state; low output impedance
• Extremely high input resistance; nearly zero steady-state input current
• No direct path steady state between power and ground; no static power
dissipation
• Propagation delay function of load capacitance and resistance of
transistors

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 Switch Delay Model
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NAND2 INV
NOR2
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Input Pattern Effects on Delay
• Delay is dependent on the pattern of
Rp Rp inputs
A B • Low to high transition
 both inputs go low
Rn CL  delay is 0.69 Rp/2 CL
B  one input goes low
 delay is 0.69 Rp CL
Rn
Cint
A
• High to low transition
 both inputs go high
 delay is 0.69 2Rn CL

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 Delay Dependence on Input Patterns

3 Input Data Delay

A=B=10 Pattern (psec)
2.5
A=B=01 67
2 A=1 0, B=1
A=1, B=01 64
Voltage [V]

1.5
A=1, B=10 A= 01, B=1 61
1
A=B=10 45
0.5
A=1, B=10 80
0
0 100 200 300 400 A= 10, B=1 81
-0.5

time [ps] NMOS = 0.5m/0.25 m

PMOS = 0.75m/0.25 m
CL = 100 fF
Transistor Sizing
Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

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Transistor Sizing a Complex CMOS Gate
B 4
A 2 3
C 4

D 4
OUT = D + A • (B + C)
A 2
D 1
B 1 C 1

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 Fan-In Considerations
A B C D

A CLDistributed RC model
(Elmore delay)
B C3
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C C2
Propagation delay deteriorates rapidly as a function of fan-in –
D C1 quadratically in the worst case.

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 tp as a Function of Fan-In
1250
quadratic
1000
Gates with a fan-in greater
750 than 4 should be avoided.
tp (psec)

tpHL tp
500

250 tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

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 tp as a Function of Fan-Out

All gates have the same

drive current.
tpNOR2 tpNAND2

tpINV
tp (psec)

Slope is a function of
“driving strength”

2 4 6 8 10 12 14 16
eff. fan-out

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tp as a Function of Fan-In and Fan-Out
• Fan-in: quadratic due to increasing resistance and capacitance

• Fan-out: each additional fan-out gate adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

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