Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

Designing Sequential
Logic Circuits
November 2002
© Digital Integrated Circuits2nd
Sequential Circuits
 Sequential Logic
Inputs Outputs
COMBINATIONAL
LOGIC

Current State
Next state
Registers
Q D

CLK

2 storage mechanisms
• positive feedback
• charge-based

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Sequential Circuits
 Naming Conventions
 In our text:
 a latch is level sensitive
 a register is edge-triggered
 There are many different naming
conventions
 For instance, many books call edge-
triggered elements flip-flops
 This leads to confusion however

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Sequential Circuits
 Latch versus Register
 Latch  Register
stores data when stores data when
clock is low clock rises

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

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Sequential Circuits
 Latches
Positive Latch Negative Latch

In D Q Out In D Q Out
G G

CLK CLK

clk clk

In In

Out Out

Out Out Out Out

stable follows In stable follows In

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Sequential Circuits
 Latch-Based Design
• N latch is transparent • P latch is transparent
when  = 0 when  = 1


N P
Logic
Latch Latch

Logic

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Sequential Circuits
 Timing Definitions

CLK
t Register
tsu t hold D Q

D DATA CLK
STABLE t
tc 2 q

Q DATA
STABLE t

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Sequential Circuits
 Characterizing Timing

tD 2 Q

D Q D Q

Clk Clk

tC 2 Q tC 2 Q

Register Latch

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Sequential Circuits
 Maximum Clock Frequency


FF’s

LOGIC Also:
tcdreg + tcdlogic > thold
tp,comb
tcd: contamination delay =
minimum delay
tclk-Q + tp,comb + tsetup = T

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Sequential Circuits
 Positive Feedback: Bi-Stability
Vi1 Vo1 = Vi2 Vo 2

V o1 Vi2
Vo 2 = Vi1

Vi1 V o2

A
Vi 2 = V o1

B
Vi 1 = V o2

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Sequential Circuits
 Meta-Stability
A A
Vi2 5 Vo1

Vi2 5 Vo1
C C

B B
Vi1 5 Vo2 Vi1 5 Vo2
d d
Gain should be larger than 1 in the transition region

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Sequential Circuits
 Writing into a Static Latch
Use the clock as a decoupling signal,
that distinguishes between the transparent and opaque states
CLK
CLK

Q D D
CLK
CLK
D

CLK
Forcing the state
Converting into a MUX (can implement as NMOS-only)

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Sequential Circuits
 Mux-Based Latches
Negative latch
Positive latch
(transparent when CLK= 0)
(transparent when CLK= 1)

Q 0 Q
1

D 0 D 1

CLK CLK

Q  Clk  Q  Clk  In Q  Clk  Q  Clk  In

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Sequential Circuits
 Mux-Based Latch
CLK

CLK

CLK

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Sequential Circuits
 Mux-Based Latch

CLK
QM
CLK

QM

CLK

CLK

NMOS only Non-overlapping clocks

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Sequential Circuits
 Master-Slave (Edge-Triggered)
Register
Slave
Master

0 Q D
1 QM
1
QM
D 0 Q

CLK
CLK

Two opposite latches trigger on edge

Also called master-slave latch pair

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Sequential Circuits
 Master-Slave Register
Multiplexer-based latch pair

I2 T2 I3 I5 T4 I6 Q

QM
D I1 T1 I4 T3

CLK

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Sequential Circuits
 Clk-Q Delay

2.5
CLK

1.5
Volts

D
tc 2 q(lh) tc 2 q(hl)
Q
0.5

2 0.5
0 0.5 1 1.5 2 2.5
time, nsec

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup Time
3.0 3.0
Q
2.5 2.5

2.0 QM 2.0 I2 2 T 2

1.5 1.5 Q
CLK CLK

Volts
Volts

D D
1.0 1.0
I2 2 T 2 QM
0.5 0.5

0.0 0.0

2 0.5 2 0.5
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
time (nsec) time (nsec)
(a) T setup 5 0.21 nsec (b) T setup 5 0.20 nsec

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Sequential Circuits
 Reduced Clock Load
Master-Slave Register

CLK CLK

D T1 I1 T2 I3 Q

I2 I4
CLK CLK

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Sequential Circuits
 Avoiding Clock Overlap
CLK X CLK
Q
A
D
B

CLK CLK
(a) Schematic diagram

CLK

CLK
(b) Overlapping clock pairs

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Sequential Circuits
 Overpowering the Feedback Loop ─
Cross-Coupled Pairs
NOR-based set-reset

S R Q Q
S
Q
S Q 0 0 Q Q
1 0 1 0
R Q
0 1 0 1
Q
R 1 1 0 0

Forbidden State

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Sequential Circuits
 Cross-Coupled NAND
Added clock
Cross-coupled NANDs VDD

S M2 M4
Q
Q
Q

Q CLK M6 M8 CLK
R M1 M3

S M5 M7 R

This is not used in datapaths any more,

but is a basic building memory cell

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Sequential Circuits
 Sizing Issues
2.0 3
Q S

1.5
2 W = 0.5 m
Q (Volts)

W = 0.6 m

Volts
1.0
W = 0.7 m
1
0.5 W = 0.8 m
W = 0.9 m
W = 1 m
0.0 0
2.0 2.5 3.0 3.5 4.0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
W/L5 and 6 time (ns)
(a) (b)

Output voltage dependence Transient response

on transistor width

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Sequential Circuits
 Storage Mechanisms

Static Dynamic (charge-based)

CLK
CLK

D Q
Q

CLK
CLK
D

CLK

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Sequential Circuits
 Making a Dynamic Latch Pseudo-Static

CLK

D D

CLK

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Sequential Circuits
 More Precise Setup Time
Clk

t
D

t
Q

1.05tC 2 Q
tC 2 Q

tSu tD 2 C

tH

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Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1

CP
TClk-Q

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1

CP
TClk-Q

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1

CP
TClk-Q

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM
D

Inv1
TClk-Q

CP

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)
CN

TG1
Inv2 Clk-Q Delay
D1 SM QM TClk-Q
D

Inv1

CP

TSetup-1 Time

Data Clock
TSetup-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1

0
CP
TClk-Q

THold-1
Time

Clock Data
THold-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1

0
CP
TClk-Q

THold-1
Time

Clock Data
THold-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1

0
CP TClk-Q

THold-1
Time

Clock Data
THold-1

Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2
D1 SM QM
D

Inv1 TClk-Q

0
CP

THold-1
Time

Clock Data
THold-1
Time
t=0

© Digital Integrated Circuits2nd

Sequential Circuits
 Setup/Hold Time Illustrations
Hold-1 case
CN

TG1 Clk-Q Delay

Inv2 TClk-Q
D1 SM QM
D

Inv1

0
CP

THold-1
Time

Clock Data
THold-1 
Time
t=0

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Sequential Circuits
 Other Latches/Registers: C2MOS
VDD VDD

M2 M6

CLK M4 CLK M8
X
D Q
CL1 CL2
CLK M3 CLK M7

M1 M5

Master Stage

“Keepers” can be added to make circuit pseudo-static

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Sequential Circuits
 Insensitive to Clock-Overlap
VDD VDD VDD VDD

M2 M6 M2 M6

0 M4 0 M8
X X
D Q D Q
1 M3 1 M7

M1 M5 M1 M5

(a) (0-0) overlap (b) (1-1) overlap

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Sequential Circuits
 Pipelining
REG

REG
a a

REG

REG

REG
REG
log Out CLK log Out
CLK

REG
REG

b CLK b CLK CLK CLK

CLK CLK

Reference Pipelined

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Sequential Circuits
 Other Latches/Registers: TSPC
VDD VDD VDD VDD

Out

In CLK CLK In CLK CLK

Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

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Sequential Circuits
 Including Logic in TSPC
VDD VDD VDD VDD

In1 In2
PUN
Q Q

In CLK CLK CLK CLK

In1
PDN

Example: logic inside the latch

AND latch

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Sequential Circuits
 TSPC Register
VDD VDD VDD

CLK Q
M3 M6 M9
Y
Q
D CLK X CLK
M2 M5 M8

CLK
M1 M4 M7

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Sequential Circuits
 Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:

Master-Slave Pulse-Triggered Latch

Latches
L1 L2 L
Data Data
D Q D Q D Q

Clk Clk Clk Clk

Clk

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Sequential Circuits
 Pulsed Latches
VDD VDD

M3 M6 VDD
CLK
Q
D CLKG CLKG MP CLKG
M2 M5
X

MN
M1 M4

(a) register (b) glitch generation

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Sequential Circuits
 Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

CLK P1 P3
x Q

M6
M3

D P2 M5
M2

M4
M1

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Sequential Circuits
 Hybrid Latch-FF Timing

3.0

2.5

2.0 D Q

1.5
Volts

1.0

0.5 CLK CLKD

0.0

20.5
0.0 0.2 0.4 0.6 0.8 1.0
time (ns)
© Digital Integrated Circuits2nd
Sequential Circuits
 Latch-Based Pipeline

CLK CLK CLK

In Out
F G
C1 C2 C3

CLK

CLK

Compute F compute G

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Sequential Circuits
 Non-Bistable Sequential Circuits─
Schmitt Trigger
Vou t V OH
In Out

•VTC with hysteresis V OL

•Restores signal slopes

VM– VM+ Vi n

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Sequential Circuits
 Noise Suppression using Schmitt
Trigger
Vin Vout

VM

VM

t0 t t 0 + tp t

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Sequential Circuits
 CMOS Schmitt Trigger
VDD

M2 M4

Vin X Vout

M1 M3

Moves switching threshold

of the first inverter

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Sequential Circuits
 Schmitt Trigger Simulated VTC

2.5 2.5

2.0 2.0

1.5 VM1 1.5

1.0 VM2 1.0

k=1
k=3
k=2
0.5 0.5
k=4

0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
Vin (V) Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the
PMOS device M4 . The width isk * 0.5 m m.

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Sequential Circuits
 CMOS Schmitt Trigger (2)
VDD

M4

M6
M3

In Out

M2
X M5
VDD

M1

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Sequential Circuits
 Multivibrator Circuits
R

S
Bistable Multivibrator
flip-flop, Schmitt Trigger

T
Monostable Multivibrator
one-shot

Astable Multivibrator
oscillator

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Sequential Circuits
 Transition-Triggered Monostable

In
DELAY
Out
td td

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Sequential Circuits
 Monostable Trigger (RC-based)
VDD

In R
A B Out

(a) Trigger circuit.

C

In

B VM
(b) Waveforms.

Out
t
t1 t2

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Sequential Circuits
 Astable Multivibrators (Oscillators)
0 1 2 N-1

Ring Oscillator
3.0
V1 V3 V5
2.5
2.0
1.5
Volts

1.0
0.5
0.0
20.5
0.0 0.5 1.0 1.5
time (ns)

simulated response of 5-stage oscillator

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Sequential Circuits
 Relaxation Oscillator
Out1
Out2
I1 I2

R C

Int

T = 2 (log3) RC

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Sequential Circuits
 Voltage Controller Oscillator (VCO)
Schmitt Trigger
VD D VDD
restores signal slopes
M6 M4

M2
In
M1
Iref Iref

Vcontr M3
M5 Current starved inverter

6
t pH L (nsec)

propagation delay as a function

0.0
0.5 1.5
V co ntr (V)
2.5 of control voltage

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Sequential Circuits
 Differential Delay Element and VCO

Vo 2 Vo 1 v3
v 1
in 1 in 2
v 2
v4

V ctrl

delay cell two stage VCO

3.0
V1 V2 V3 V4
2.5

2.0

1.5

1.0

0.5

0.0

2 0.5
0.5 1.5 2.5 3.5
time (ns)

simulated waveforms of 2-stage VCO

© Digital Integrated Circuits2nd

Sequential Circuits