MCU2101

Getting Started with

Microchip PIC18 Architecture

Authors: Mark Reynolds, TTM & Rob Ostapiuk, TTM

 Agenda

Architecture Basics
Instruction Pipelining
Long Word Instructions
Instruction Set Overview
Memory Organization and Addressing
Modes
Special Features
Hands-on Exercises

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 2

 Class Objective

When you finish this class you will:

– Understand the basics of the inner workings
of a PIC18
– Understand most instructions
– Understand memory organization
– Understand how to write simple programs

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 3

 Architecture
The high performance of the PICmicro® microcontroller
can be attributed to the following architectural features:
Harvard Architecture
Instruction Pipelining
Large Register File
Single Cycle Instructions
Single Word Instructions
Long Word Instructions
Reduced Instruction Set
Orthogonal Instruction Set

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 4

 Harvard Architecture
Von Neumann Von Neumann
Architecture Architecture:
Fetches instructions and
data from a single memory
space
8-bit Bus Program Limits operating bandwidth
& Data
Memory
CPU
Harvard Architecture:
Harvard Uses two separate memory
Architecture
spaces for program
instructions and data
8-bit Bus Data Improved operating
Memory
bandwidth
CPU
16-bit Bus
Allows for different bus
Program
widths
Memory

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 5

 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

movlw 0x05 -
Instruction Cycles

T0
Example Program
1 MAIN movlw 0x05 Fetch

2 movwf REG1
3 rcall SUB1
4 addwf REG2

51 SUB1 movf PORTB,w

52 return
53 SUB2 movf PORTC,w
54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 6
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

movwf REG1 movlw 0x05

Instruction Cycles

T0 T1
Example Program
1 MAIN movlw 0x05 Fetch Execute

2 movwf REG1 Fetch

3 rcall SUB1
4 addwf REG2

51 SUB1 movf PORTB,w

52 return
53 SUB2 movf PORTC,w
54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 7
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

rcall SUB1 movwf REG1

Instruction Cycles

T0 T1 T2
Example Program
1 MAIN movlw 0x05 Fetch Execute Time to execute normal instruction

2 movwf REG1 Fetch Execute

3 rcall SUB1 Fetch

4 addwf REG2

51 SUB1 movf PORTB,w

52 return
53 SUB2 movf PORTC,w
54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 8
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

addwf REG2 rcall SUB1

Instruction Cycles

T0 T1 T2 T3
Example Program
1 MAIN movlw 0x05 Fetch Execute

2 movwf REG1 Fetch Execute

3 rcall SUB1 Fetch Execute

4 addwf REG2 Fetch

51 SUB1 movf PORTB,w

52 return
53 SUB2 movf PORTC,w
54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 9
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

movf PORTB,w rcall SUB1

Instruction Cycles

T0 T1 T2 T3 T4
Example Program
1 MAIN movlw 0x05 Fetch Execute

2 movwf REG1 Fetch Execute Time to execute call

instruction includes
3 rcall SUB1 Fetch Execute pipeline flush

4 addwf REG2 Fetch Flush

51 SUB1 movf PORTB,w Fetch

52 return
53 SUB2 movf PORTC,w
54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 10
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

return movf PORTB,w

Instruction Cycles

T0 T1 T2 T3 T4 T5
Example Program
1 MAIN movlw 0x05 Fetch Execute

2 movwf REG1 Fetch Execute

3 rcall SUB1 Fetch Execute

4 addwf REG2 Fetch Flush

51 SUB1 movf PORTB,w Fetch Execute

52 return Fetch

53 SUB2 movf PORTC,w

54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 11
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

movf PORTC,w return

Instruction Cycles

T0 T1 T2 T3 T4 T5 T6
Example Program
1 MAIN movlw 0x05 Fetch Execute

2 movwf REG1 Fetch Execute

3 rcall SUB1 Fetch Execute

4 addwf REG2 Fetch Flush

51 SUB1 movf PORTB,w Fetch Execute

52 return Fetch Execute

53 SUB2 movf PORTC,w Fetch

54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 12
 Instruction Pipelining
Pre-Fetched Instruction Executing Instruction

addwf REG2 return

Instruction Cycles

T0 T1 T2 T3 T4 T5 T6 T7
Example Program
1 MAIN movlw 0x05 Fetch Execute

2 movwf REG1 Fetch Execute

3 rcall SUB1 Fetch Execute

4 addwf REG2 Fetch Flush Fetch

51 SUB1 movf PORTB,w Fetch Execute

52 return Fetch Execute

53 SUB2 movf PORTC,w Fetch Flush

54 return
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 13
 Long Word Instruction
8-bit Program Memory 8-bit Instruction on typical 8-bit MCU
Example: Freescale ‘Load Accumulator A’:
• 2 Program Memory Locations
• 2 Instruction Cycles to Execute

ldaa #k
Limits Bandwidth
1 0 0 0 0 1 1 0
Increases Memory Size
k k k k k k k k Requirements

16-bit Program Memory

16-bit Instruction on PIC18 8-bit MCU
Example: ‘Move Literal to Working Register’
• 1 Program Memory Location
• 1 Instruction Cycle to Execute

movlw k
0 0 0 0 1 1 1 0 k k k k k k k k

 Separate busses allow different widths

 2k x 16 is roughly equivalent to 4k x 8

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 14

 PIC18 Instruction Set Overview
Byte Oriented Operations negf f,a Negate f
addwf f,d,a Add WREG and f rlcf f,d,a Rotate Left f through Carry
addwfc f,d,a Add WREG and Carry bit to f rlncf f,d,a Rotate Left f (No Carry)
andwf f,d,a AND WREG with f rrcf f,d,a Rotate Right f through Carry
clrf f,a Clear f rrncf f,d,a Rotate Right f (No Carry)
comf f,d,a Complement f setf f,a Set f
cpfseq f,a Compare f with WREG, skip = subfwb f,d,a Subtract f from WREG with borrow
cpfsgt f,a Compare f with WREG, skip > subwf f,d,a Subtract WREG from f
cpfslt f,a Compare f with WREG, skip < subwfb f,d,a Subtract WREG from f with borrow
decf f,d,a Decrement f swapf f,d,a Swap nibbles in f
decfsz f,d,a Decrement f, Skip if 0 tstfsz f,a Test f, skip if 0
dcfsnz f,d,a Decrement f, Skip if Not 0 xorwf f,d,a Exclusive OR WREG with f
incf f,d,a Increment f
incfsz f,d,a Increment f, Skip if 0
infsnz f,d,a Increment f, Skip if Not 0 Bit Oriented Operations
iorwf f,d,a Inclusive OR WREG with f bcf f,b,a Bit Clear f
movf f,d,a Move f bsf f,b,a Bit Set f
movff fss,fdd Move fss (src) to fdd (dst) btfsc f,b,a Bit Test f, Skip if Clear
movwf f,a Move WREG to f btfss f,b,a Bit Test f, Skip if Set
mulwf f,a Multiply WREG with f btg f,b,a Bit Toggle f

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 15

 PIC18 Instruction Set Overview
Control Operations Literal Operations
bc n Branch if Carry addlw k Add literal and WREG
bn n Branch if Negative andlw k AND literal with WREG
bnc n Branch if Not Carry iorlw k Inclusive OR literal with WREG
bnn n Branch if Not Negative lfsr f,k Move 12-bit literal to FSR
bnov n Branch if Not Overflow movlb k Move literal to BSR<3:0>
bnz n Branch if Not Zero movlw k Move literal to WREG
bov n Branch if Overflow mullw k Multiply literal with WREG
bra n Branch Always retlw k Return with literal in WREG
bz n Branch if Zero sublw k Subtract WREG from literal
call n,s Call subroutine xorlw k Exclusive OR literal with WREG
clrwdt Clear Watchdog Timer
daw Decimal Adjust WREG
goto n Go to address Data Memory  Program Memory Operations
nop No Operation tblrd* Table Read
pop Pop top of return stack (TOS) tblrd*+ Table Read with post-increment
push Push top of return stack (TOS) tblrd*- Table Read with post-decrement
rcall n Relative Call tblrd+* Table Read with pre-increment
reset Software device RESET tblwt* Table Write
retfie s Return from interrupt tblwt*+ Table Write with post-increment
return s Return from subroutine tblwt*- Table Write with post-decrement
sleep Go into standby mode tblwt+* Table Write with pre-increment

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 16

 Instruction Set Overview

Byte Oriented Operations

15 9 8 7 0

Opcode a f f f f f f f f
OR
Opcode d a f f f f f f f f
File Register Address
Destination (W or F) Access Bank

ADDWF 0x25, W, A
File Register Address Use Access Bank
Destination (Optional)

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 17

 Instruction Set Overview

Bit Oriented Operations

15 11 9 8 7 0

Opcode b b b a f f f f f f f f
File Register Address

Bit Position (0-7)

BSF 0x25, 3, A
File Register Address Access Bank
Bit Position (Optional)

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 18

 Instruction Set Overview

Literal and Control Operations

15 8 7 Literal Value 0

Opcode k k k k k k k k
OR
Opcode

MOVLW 0x25
Literal Value

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 19

 Instruction Set Overview

Byte to Byte Move Operations(2 Words)

15 12 11 Source Register Address 0

Opcode f s f s f s fs fs fs fs f s fs f s fs f s
Opcode f d f d f d fd fd f d fd f d fd f d fd fd
Destination Register Address

MOVFF 0x125, 0x140

Source Address Destination Address

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 20

 Instruction Set Overview

Call and Goto Operations (2 Words)

15 11 8 7 0

Opcode n8 n7 n6 n5 n4 n3 n2 n1

Opcode n20 n19 n18 n17 n16 n15 n14 n13 n12 n11 n10 n9

CALL 0x1125
Subroutine Address

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 21

 ALU Datapath
Output to Working Register
ALU output can be stored in
Working register or data memory
W Register Data Memory
02 01
01 20h : myVal
21h
22h

ALU

addwf myVal,W
1) Adds the Working register and “myVal” then …

ALU = Arithmetic Logic Unit

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 22
 ALU Datapath
Output to Working Register
ALU output can be stored in
Working register or data memory
W Register Data Memory
03 01
01 20h : myVal
21h
22h

ALU

addwf myVal,W
1) Adds the Working register and “myVal” then …
2) Stores the result in the Working register
ALU = Arithmetic Logic Unit
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 23
 ALU Datapath
Output to File Register
ALU output can be stored in
Working register or data memory
W Register Data Memory
02 01
01 20h : myVal
21h
22h

ALU

addwf myVal,F
1) Adds the Working register and “myVal” then …

ALU = Arithmetic Logic Unit

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 24
 PIC18 Addressing Modes

Data Memory Access:

Mode Example Syntax
Direct clrf <reg>, <dst>
Indirect clrf INDFn, <dst>
Auto Pre-Increment
movff PREINCn, <dst>
Indirect
Auto Post-
movff POSTINCn, <dst>
Increment Indirect
Auto Post-
movff POSTDECn, <dst>
Decrement Indirect
Index Indirect movff PLUSWn, <dst>
Immediate (Literal) movlw <const>

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 25

 Data Memory Organization
000h
Access RAM PIC16F8F2520/4520
07Fh
Data Memory up to 080h
Bank 0 GPR
Register File Map
0FFh
4k bytes 100h
Bank 1
Divided into 256 1FFh
GPR

byte banks 200h

Bank 2
GPR Access Bank
Half of bank 0 and 2FFh
00h
Access RAM
half of bank 15 7Fh
80h
Access SFR
form a virtual bank D00h
Bank 13
FFh

256 Bytes
that is accessible DFFh
GPR

no matter which E00h

Bank 14
bank is selected EFFh
GPR

F00h
Bank 15 GPR
F7Fh
F80h
FFFh Access SFR
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 26
 SFR Register Map
Bank 15
UPPER ADDRESS BITS

00h - Unused register read as all zeros

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 27

 Register Direct Addressing
‘a’ Bit from BSR ‘f’ Operand
Instruction 12-bit Effective Address
4-bits from BSR Register 8-bits Encoded in Instruction (Use this when coding)

0 0 0 1 0 0 1 1 1 1 1 1 0 0x27E
Bank0 Bank1 Bank2 Bank13 Bank14 Bank15
00 FF FF
FF FF
FF FF
FF FF FF
01 FF FF
FF FF
FF FF
FF FF FF
02 FF FF
FF FF
FF FF
FF FF FF
03 FF FF
FF FF
FF FF
FF FF FF

7D FF FF
FF FF
FF FF
FF FF FF
7E FF FF
FF FF FF
FF FF FF
7F FF FF
FF FF
FF FF
FF FF FF
80 FF FF
FF FF
FF FF
FF FF FF
81 FF FF
FF FF
FF FF
FF FF FF
82 FF FF
FF FF
FF FF
FF FF FF

FC FF FF
FF FF
FF FF
FF FF FF
FD FF FF
FF FF
FF FF
FF FF FF
FE FF FF
FF FF
FF FF
FF FF FF
FF FF FF
FF FF
FF FF
FF FF FF

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 28

 Register Direct Addressing
‘a’ Bit from BSR ‘f’ Operand
Instruction 12-bit Effective Address
4-bits from BSR Register 8-bits Encoded in Instruction (Use this when coding)

0 1 1 0 1 0 1 1 1 1 1 1 0 0xD7E
Bank0 Bank1 Bank2 Bank13 Bank14 Bank15
00 FF FF
FF FF
FF FF
FF FF FF
01 FF FF
FF FF
FF FF
FF FF FF
02 FF FF
FF FF
FF FF
FF FF FF
03 FF FF
FF FF
FF FF
FF FF FF

7D FF FF
FF FF
FF FF
FF FF FF
7E FF FF
FF FF
FF FF FF FF
7F FF FF
FF FF
FF FF
FF FF FF
80 FF FF
FF FF
FF FF
FF FF FF
81 FF FF
FF FF
FF FF
FF FF FF
82 FF FF
FF FF
FF FF
FF FF FF

FC FF FF
FF FF
FF FF
FF FF FF
FD FF FF
FF FF
FF FF
FF FF FF
FE FF FF
FF FF
FF FF
FF FF FF
FF FF FF
FF FF
FF FF
FF FF FF

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 29

 Register Direct Addressing
‘a’ Bit from BSR ‘f’ Operand
Instruction 12-bit Effective Address
4-bits from BSR Register 8-bits Encoded in Instruction (Use this when coding)

1 XXXX 1 0 0 0 0 0 1 0 0xF82
Bank0 Bank1 Bank2 Bank13 Bank14 Bank15
00 FF FF
FF FF
FF FF
FF FF FF
01 FF FF
FF FF
FF FF
FF FF FF
02 FF FF
FF FF
FF FF
FF FF FF
03 FF FF
FF FF
FF FF
FF FF FF

7D FF FF
FF FF
FF FF
FF FF FF
7E FF FF
FF FF
FF FF
FF FF FF
7F FF FF
FF FF
FF FF
FF FF FF
80 FF FF
FF FF
FF FF
FF FF FF
81 FF FF
FF FF
FF FF
FF FF FF
82 FF FF
FF FF
FF FF
FF FF FF

FC FF FF
FF FF
FF FF
FF FF FF
FD FF FF
FF FF
FF FF
FF FF FF
FE FF FF
FF FF
FF FF
FF FF FF
FF FF FF
FF FF
FF FF
FF FF FF

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 30

 Register Direct Addressing
‘a’ Bit from BSR ‘f’ Operand
Instruction 12-bit Effective Address
4-bits from BSR Register 8-bits Encoded in Instruction (Use this when coding)

0 0 0 0 1 1 0 0 0 0 0 1 0 0x182
Bank0 Bank1 Bank2 Bank13 Bank14 Bank15
00 FF FF
FF FF
FF FF
FF FF FF
01 FF FF
FF FF
FF FF
FF FF FF
02 FF FF
FF FF
FF FF
FF FF FF
03 FF FF
FF FF
FF FF
FF FF FF

7D FF FF
FF FF
FF FF
FF FF FF
7E FF FF
FF FF
FF FF
FF FF FF
7F FF FF
FF FF
FF FF
FF FF FF
80 FF FF
FF FF
FF FF
FF FF FF
81 FF FF
FF FF
FF FF
FF FF FF
82 FF FF FF
FF FF
FF FF

FC FF FF
FF FF
FF FF
FF FF FF
FD FF FF
FF FF
FF FF
FF FF FF
FE FF FF
FF FF
FF FF
FF FF FF
FF FF FF
FF FF
FF FF
FF FF FF

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 31

 Program Memory Organization
Reset Vector 000000h

One, contiguous linear program High Priority Interrupt Vector 000008h

memory space up to 2MB Low Priority Interrupt Vector 000018h

(1MWord)
21-bit Program Counter
On-chip Program Memory

Stack Level 1
007FFEh
Stack Level 2
008000h

Stack Level 30
Stack Level 31
Unimplemented
31 Level Stack Program Memory
(Read as ‘0’)

1FFFFEh

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 32

Program Memory is Byte Addressable

Low byte has even address, high byte has odd

address
Addresses of instructions are always even
Word Address
High Byte Address 16-bit Program Memory Low Byte Address

0x000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000

0x000003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000002

0x000005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000004

0x000007 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000006

0x000009 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000008

0x00000B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000A

0x00000D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000C

0x00000F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000E

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 33

 Program Counter
PCU PCH PCL
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Program Counter

21-bit PC can access up to 221 = 2MB (1MWord)

22nd bit used to access configuration memory at
program time or via table reads & writes
Contains address of NEXT instruction (pipelining)
Lower byte accessible in data memory as PCL
Upper bytes indirectly accessible via PCLATH/PCLATU
Bit 0 of PC is always ‘0’ except when reading or writing
program memory via table read/write mechanism
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 34
 PC Absolute Addressing
CALL and GOTO Instructions:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit 0 of the address
n
n88 n
n n n n n n n11 n0
n n is implied since it is
always zero due to
1 11 1 11 n
n n
n n n
n n
n n n
20
20 n n n n n99
n n n the byte
addressability of
program memory
n = Program Memory Address

PC Absolute Addressing (Program Memory)

Jump to another program memory location out of PC sequence
Call a subroutine
Used by the CALL and GOTO instructions
Full address is specified as part of the two word instruction
Used when performing Computed Goto operation
Address to jump to is calculated by the program
Computed address is written directly into the Program Counter

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 35

 PC Relative Addressing: Branch
Instructions
Used by single word branch instructions:
BC / BNC: -128  n  127
BN / BNN: -128  n  127
BOV / BNOV: -128  n  127
BZ / BNZ: -128  n  127
BRA: -1024  n  1023
RCALL: -1024  n  1023

n is the relative offset from the PC

Example: BC CarryBitSet
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 36
 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0

STKPTR [SP4:SP0] PC 01
Register

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 37

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0

STKPTR [SP4:SP0]
PC
Register
PC 01

call

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 38

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0

STKPTR [SP4:SP0] PC
Register
PC
PC 01

Interrupt

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 39

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0
STKPTR [SP4:SP0]
Pushed Data
Register PC
PC
PC 01

push

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 40

 PIC18 Hard Stack
Top of Stack Register
STKPTR [SP4:SP0] 31
TOSU TOSH TOSL
Current value on the
Register Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

1 0 X
7 6 5 4 0

Pushed Data
PC
PC
PC 01

Over Flow Error

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 41

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0

STKPTR [SP4:SP0] PC
Register
PC
PC 01

pop

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 42

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0

STKPTR [SP4:SP0]
PC
Register
PC 01

RETFIE

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 43

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 0 X
7 6 5 4 0

STKPTR [SP4:SP0] PC 01
Register

return

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 44

 PIC18 Hard Stack
Top of Stack Register
TOSU TOSH TOSL
31 Current value on the
Top Of Stack
23 0

STKPTR Register
STKOVFSTKUNF SP4:SP0

0 1 X
7 6 5 4 0

PC 01
STKPTR [SP4:SP0]
Register Under Flow Error

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 45

Special Features
Overview
 PIC18 Oscillator Options
XT Standard frequency crystal oscillator 100kHz - 4MHz
HS High frequency crystal oscillator DC - 40MHz
HS+PLL High frequency crystal with 4x PLL 4MHz - 10MHz
LP Low frequency crystal oscillator 5kHz - 200kHz
RC External RC oscillator DC - 4MHz
RCIO External RC oscillator, OSC2=RA6 DC - 4MHz
INTRC Internal RC oscillator Various
EC External Clock, OSC2=fosc
osc
/4 DC - 40MHz
ECIO External Clock, OSC2=RA6 DC - 40MHz

Selectable clock options provide greater flexibility for the

designer:
LP Oscillator designed to draw least amount of current
RC or INTRC provide ultra low cost oscillator solution
XT optimized for most commonly used oscillator frequencies
HS optimized to drive high frequency crystals or resonators
Speed ranges are guidelines only

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 47

 POR, OST, PWRT
POR: Power On Reset
With MCLR tied to VDD, a reset VDD
DD

pulse is generated when VDD rise

MCLR
is detected
TPWRT
PWRT
PWRT: Power Up Timer PWRT
Device is held in reset for 72ms TOST
OST
(nominal) to allow VDD to rise to OST
an acceptable level (after POR
only)
Reset Execution
OST: Oscillator Start-up Timer
Holds device in reset for 1024
cycles to allow crystal or
resonator to stabilize in
frequency and amplitude; not
active in RC modes; used only
after POR or Wake Up from
SLEEP

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 48

 Sleep Mode
The processor can be put into a power-down
mode by executing the SLEEP instruction
System oscillator is stopped
Processor status is maintained (static design)
Watchdog timer continues to run, if enabled
Minimal supply current is drawn - mostly due to leakage (0.1 -
2.0A typical)

Events
Events that
that wake
wake processor
processor from
from sleep
sleep
MCLR Master Clear Pin Asserted (pulled low)
WDT Watchdog Timer Timeout
INT INT Pin Interrupt
TMR1 Timer 1 Interrupt (or also TMR3 on PIC18)
ADC A/D Conversion Complete Interrupt
CMP Comparator Output Change Interrupt
CCP Input Capture Event
PORTB PORTB Interrupt on Change
SSP Synchronous Serial Port (I22C Mode) Start / Stop Bit Detect Interrupt
PSP Parallel Slave Port Read or Write
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 49
 Watchdog Timer
Helps recover from software malfunction
Uses its own free-running on-chip RC oscillator
WDT is cleared by CLRWDT instruction
Enabled WDT (WDTEN) cannot be disabled by software
WDT overflow resets the chip
Programmable timeout period: 18ms to 3.0s typical
Operates in SLEEP; on time out, wakes up CPU
WDT Ripple
Postscaler
Counter

WDTEN
SWDTEN 8:1 Mux

WDT Timeout
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 50
 In-Circuit Serial Programming™
Pin
Pin Function
Function
Only two pins required for
VPP Programming Voltage = 13V
programming PP
VDD Supply Voltage
DD

Convenient for In-System VSS

SS Ground
Programming of RB6 Clock Input
RB7 Data I/O & Command Input
Calibration Data
Serialization Data
Supported by MPLAB® PM3 & ICD2
Application PCB VDD VDD

MCLR/VPP

ICSP™ Connector
ICSP Connector
PIC18Fxxxx

VDD

VSS

RB6

RB7

Isolation
To application circuit
circuits

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 51

 BOR –Brown Out Reset

 When voltage drops below a

particular threshold, the device is
held in reset
 Prevents erratic or unexpected
operation
 Eliminates need for external BOR
circuitry
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 52
PBOR – Programmable Brown Out
Reset
Configuration Option (set at program time)
Cannot be enabled / disabled in software
Four selectable BVDD trip points:
2.5V – Minimum VDD for OTP PICmicro® MCUs
2.7V
4.2V
4.5V
For other thresholds, use an external supervisor
(MCP1xx, MCP8xx/TCM8xx, or TC12xx)

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 53

PBOR – Programmable Brown Out
Reset
Holds PICmicro® MCU in reset until ~72ms after VDD rises back above threshold

VDD
BVDD

72ms
Internal
Reset

VDD
BVDD

72ms
Internal
Reset <72ms

VDD
BVDD

72ms
Internal
Reset

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 54

 PLVD – Programmable Low Voltage
Detect
VDD LVDIN
Early warning LVDCON

before brown out

16 selectable trip

16-bit Multiplexer
points:
1.8V up to 4.5V in LVDIF

0.1 to 0.2V steps

External analog
input
VREF
Internal VREF LVDIN

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 55

 I/O Ports
VDD
Data Bus D Q

High Drive Capability Write PORTx

Q

Can directly drive LEDs RESET

I/O Pin
D Q
Direct, single cycle Write TRISx
Q
bit manipulation V SS

Each pin has individual Read PORTx

direction control under software

All pins have ESD protection diodes
Pin RA4 is usually open drain
All I/O pins default to inputs (high impedance) on
startup
All pins multiplexed with analog functions default to
analog inputs on startup
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 56
 Digital I/O Ports – PIC18

Internal Data Bus

Write PORTx
Read LATx Read PORTx
Write LATx

LATx Register
(PORTx Output
Latches)

PORTx I/O Pins

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 57

 Reason for LATx Registers
At Low Frequency or Low Capacitive Loading
BSF PORTx,PINy BSF PORTx,PINz

V on PORTx,PINy Q4 Q1 Q2 Q3

VIL

t
Port Sampled in RMW Operation

At High Frequency or High Capacitive Loading

BSF PORTx,PINy BSF PORTx,PINz
V on PORTx,PINy Q4 Q1 Q2 Q3 Q4

VIL

Port Sampled in RMW Operation

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 58
 I/O Ports

I/O Pin Direction Control

TRISB 1 1 0 1 1 0 0 0

PORTB In In Out In In Out Out Out

Bit n in TRISx controls the data direction

of Bit n in PORTx
1 = Input, 0 = Output
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 59
 Analog or Digital Input?

Some I/O pins multiplexed with

analog inputs (analog by default)
Programmer is responsible for
configuring Input as either Digital or

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 60

Configuring Analog Pins for Digital
Method depends on specific device
Could be in ADCON register Port Configuration Bits
ADC Control Register 1 (ADCON1)
Could be in ADCON1 register
VCFG1
VCFG1 VCFG0
VCFG0 PCFG3
PCFG3 PCFG2
PCFG2 PCFG1
PCFG1 PCFG0
PCFG0

AN12
AN11
AN10
PCFG3:

AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCFG0

0000 A A A A A A A A A A A A A
0001 A A A A A A A A A A A A A
0010 A A A A A A A A A A A A A
0011 D A A A A A A A A A A A A

1100 D D D D D D D D D D A A A
1101 D D D D D D D D D D D A A
1110 D D D D D D D D D D D D A
1111 D D D D D D D D D D D D D

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 61

Configuring Analog Pins for Digital
Method depends on specific device
Could be in ANSEL register

Analog Select Register (ANSEL)

Analog Select High Register (ANSELH)

ANx
ANx==11for
forAnalog
Analog
ANx = 0 for Digital
ANx = 0 for Digital

** Default Value is Analog

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 62

Hands-on Exercises
Summary
 Summary

PIC18 Architecture
PIC18 Instruction Set
PIC18 Memory Organization
Simple Programming Techniques

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 65

 Resources
Microchip PIC18 material
PICmicro® 18C MCU Family Reference Manual (DS39500A)

PIC18F46K20 Data Sheet

PICDEM2 Plus Users Guide (DS51275D)

More than 100 App notes, design guides and other reference material!

www.microchip.com
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 66
 Resources

www.microchip.com/PIC18

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 67

 Reference Books
Books on PIC18

Programming and Customizing PIC Microcontrollers

3rd Edition (September 27, 2007)
Myke Predko
ISBN-10: 0071472876
ISBN-13: 987-0071472876

Embedded Design with the PIC18F452 Microcontroller

1th Edition (August 15, 2002)
John B. Peatman
ISBN-10: 0130462138
ISBN-13: 978-0130462138

PIC microcontrollers and Embedded Systems

4th Edition (October 19, 2006)
Muhammad Ali Mazidi , Rolin McKinlay, Danny Causey
ISBN-10: 0131194045
ISBN-13: 978-0131194045
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 68
 Questions?

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 69

Thank You!
 Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, KeeLoq, KeeLoq logo,
MPLAB, MPLAB X, PIC, PICmicro, PICSTART, PIC 32 logo, rfPIC and UNI/O are
registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL
and The Embedded Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE,
In‑Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo,
MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode,
Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their respective companies.

© 2011, Microchip Technology Incorporated, All Rights Reserved.

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 71