MCU3121

MCU3121

Microchip 16-bit MCU

PIC24F
Author: Bob Smith
Microchip Technology
 Objectives
When you finish this class, you will be
able to:
Differentiate between Microchip’s 16-bit MCU
and DSC families
Identify the essential tools, documentation
and support for a successful 16-bit design
Describe most 16-bit Peripheral Operations
and Configure them as desired
Analyze the SPI and I2C serial interfaces and
describe their differences

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 2

 Agenda
Brief 16-Bit Architecture & Core Overview
Essential tool, documentation & support resources
16-Bit Product Family Overview
General Purpose I/O Ports
LAB 1: General Purpose I/O Ports
Analog to Digital Converter
LAB 2: ADC
Timers
LAB 3: Timers
Input Capture
Output Compare and PWM
LAB 4: PWM
UART
LAB 5: UART

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 3

 16-bit
Architecture & Core Overview
 dsPIC and PIC24
Simplified Block Diagram
Program Space 3 Data
Visibility
Buses
DMA 16-bit DMA 16K x 16
Program
Data
Bus
Memory
PSV &
(SRAM)
Table Access
4M x 24 bit
Program
Memory Peripherals
16-bit CPU X
(Flash) 16-bit X
24-bit AGU
W Array
Y 16-bit Y I/O Ports
16 x 16
AGU

16 Accumulators Address
(Working Registers) Generation
DSP Units
Engine dsPICs
(MAC) only
Multiply Accumulate

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 5

 Program Memory Map
MSW = most significant word MSW 24 bits LSW
LSW = least significant word Address Address
MSW LSW
0x000001 Reset Vector 0x000000
Instructions occupy 0x000005 Primary Interrupt 0x000004
even addresses only. 0x0000FF Vector Table 0x0000FE
The Program Counter
always increments by 2. Alternate Interrupt
Vector Table
0x000201 0x000200
User
memory
space User Flash

Odd Program Memory

addresses are used for Data EEPROM (dsPIC30F)
writing & reading 8 bit Flash Configuration Words
data during table write
& read operations. unimplemented
0x7FFFFF 0x7FFFFE
Configuration Registers
Configuration
memory space
Device ID
0xFFFFFF 0xFFFFFE
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 6
 Data Memory Map
MSB 16-bits LSB
Address Address
MSB LSB
2 KB Special 0x0001 0x0000
Function Registers 0x07FF
Special Function Registers 0x07FE
0x0801 0x0800
NEAR
X Data RAM Data Memory
SRAM Space 8KB
DIRECTLY
0x1FFF Y Data RAM 0x1FFE ADDRESSIBLE
0x2001 0x2000 POINTERS
Dual Port
DMA RAM Dual Port RAM REQUIRED
2KB Y Data RAM found
0x8001 0x8000 only on dsPICs

Dual Port RAM found in

Optional window into devices with DMA
Program Memory Unimplemented
using Program Space
Visibility (PSV)
32KB
0xFFFF 0xFFFE

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 7

 Clocking Scheme
Converting MHz to MIPS

PIC24 and dsPIC33 dsPIC30

have 2 external clocks has 4 external clocks
per instruction cycle per instruction cycle

FOSC FOSC

External Clock
FCY FCY
Internal
Instruction Clock
PIC24 and dsPIC33 dsPIC30

FOSC = oscillator frequency PIC24F…………………16 MIPS max

PIC24H & dsPIC33F….40 MIPS max
FCY = instruction frequency
PIC24E & dsPIC33E….70 MIPS max
TCY = 1/FCY = instruction period dsPIC30………………..30 MIPS max

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 9

Essential Tools, Documentation
& Support for 16-bit designs
 Essential 16-bit Tools
Hardware
Explorer 16 Evaluation Board
Includes PICtail Plus interface for expansion
Add PICtail Plus daughter boards for USB,
Ethernet, Graphics, Wireless, etc…

Microstick Evaluation Board

Includes programmer/debugger on board

Many other 16-bit Eval Boards found here:

www.microchip.com/DTS

Programmer/Debuggers

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 11

 Essential 16-bit Tools
Software

MPLAB® IDE
www.microchip.com/mplab

MPLAB® C Compiler for PIC24

Free version with low level optimizations available
www.microchip.com/compilers

16-bit Peripheral Libraries

C source code to facilitate
the following:
Working with 16-bit peripherals
DSP functions
Math functions
Included with free C compiler
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 12
 Essential 16-bit Tools
Documentation – Device Data Sheets and FRM

Device data sheets

Specifies device pinouts, electrical specs & packaging
Only high-level descriptions of core and peripherals

16-bit Family Reference Manual

(FRM)
Detailed descriptions of Core and
Peripherals
Each chapter is a separate PDF file

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 13

 Essential 16-bit Tools
Documentation – Device Header Files

Defines Special Function

Register (SFR) names

Defines SFR
bit-field names
Defines SFR
bit names
Defines SFR bit
name shortcuts

Defines useful
macros

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 14

 Essential 16-bit Tools
Support
Technical Support via Web Tickets
www.microchip.com/support
16-bit Forums
www.microchip.com/forums
Embedded Code Source
Code examples for Microchip micros
www.embeddedcodesource.com
Application Notes
www.microchip.com/appnotes
16-bit Products Page
www.microchip.com/16bit

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 15

 16-bit Product Families
Which peripherals are included in each product family?
PIC® MCU Families

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 17

 PIC24F Family
Low Power & Low Cost MCU
PIC24F Core (Up to 16 MIPS)

Peripheral
Pin Select

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 18

 MAPS
Microchip’s Advanced Part Selector

There are over 250 16-bit devices to choose from

Use “MAPS” to narrow the list:
www.microchip.com/MAPS

Enter your device

requirements

See list of parts meeting

these requirements

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 19

Input / Output Ports
TRIS (Data Direction) Registers

Data Direction
TRISx 0 1 0 1 0 0 1 1 (1 = IN, 0 = OUT)

PORTx

Device Pins

All I/O pins are initialized as inputs

after a reset (TRIS = 0xFFFF)

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 21

 PORT and LAT Registers

Internal Data Bus

Write Read Read
PORTx LATx PORTx
or LATx
LATx 0 1 0 1 0 0 1 1

PORTx
The GPIO pins are
Device Pins the PORT Register
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 22
 Steps for working with I/O Ports

1 Initialize Output Write to: LATB = 0;

Latches to Known LAT LATBbits.LATB0 = 0;
State _LATB0 = 0;

2 Configure Data Write to: TRISB = 0x0023;

Direction of Pins TRIS TRISBbits.TRISB0 = 1;
_TRISB0 = 1;

3a Write to outputs Write to: LATB = 0x00F0;

LAT LATBbits.LATB0 = 0;
_LATB0 = 0;

3b Read from inputs Read from: myVar = PORTB;

PORT myVar = PORTBbits.RB0;
myVar = _RB0;

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 23

Interfacing 3.3V I/O to 5V Devices

An Open Drain Output can drive low but cannot

drive high. When the pin is not driving low it will be
in a tri-state condition. A resistor can be used to
pull up the voltage to 5V.
+3.3 V +5 V

Output
Configured with
Open Drain

5 Volt Tolerant Inputs

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 24
 Lab 1
Working with General Purpose I/O Pins (PORTS)
Analog to Digital Converter
 ADC Overview
Highest performance ADC: There are several flavors
of ADCs. See device
500 Ksps in 12 bit mode data sheet for details.
1.1 Msps in 10 bit mode
Successive Approximation (SAR) conversion
Up to 32 analog input pins
Up to 4 simultaneous samples with one ADC
Some devices have 2 ADCs
Automatic Channel Scan mode

ADC
Analog Digital
Input Output
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 27
 Simplified ADC Block Diagram
Channel Select One of many channel
CHS4:CHS0 select options

AN32
Configurable 16
AN31
Word Result Buffer
1 or 4 (SFRs found in DM)
• Sample Caps
•
•
32:1 Analog Mux

•
•
AN7
AN6
AN5
ADC ADCxBUF0
ADCxBUF1
AN4 •
VREFL •
AN3 VREFH VREFL •
AN2 ADCxBUFF
AVDD
AN1
AN0
VREF+
VREF-

AVSS
See device data sheet Multiple Voltage
for # of ADC channels Reference options
VCFG2:VCFG0
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 28
 ADC Sample Time

Can be measured Sample Time

in terms of TAD
time
TAD
Charge time is determined by
the circuit’s RC time constant VC
VIN

time

SOURCE
RS < 10k
ADC
+ Sample Time allows V
CHOLD VC Hold Capacitor to
- fully charge to VIN
VREFL
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 29
 ADC Conversion Time
Total Acquisition Time
Sample Time Conversion Time

TAD configured to be
time
minimum time to convert TAD
one bit in SAR ADC cycle
VC
VIN

time
Conversion auto-starts
when sampling stops

ADC Total Conversion time = TAD x (# of bits + 2)

+
CHOLD VC
-
VREFL
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 30
 Generating the ADC clock period (TAD)
ADCS<7:0>
Configure TAD to be close to,
8
but not less than the
TCY ADC Clock minimum TAD
Postscaler TAD min is in the 35nS to 133nS
÷ by 1 to 256 TAD range (see data sheet)

Internal
instruction RCAD The minimum TAD time
rate
comes from the minimum
ADRC
Internal ADC RC time to convert one bit in
oscillator (4MHz Typ)
the SAR ADC process
ADC Control Register #3 (AD1CON3)
15 14 13 12 11 10 9 8
If the ADC RC
ADRC SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 oscillator is used,
7 6 5 4 3 2 1 0 TAD = 250ns
ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 31

 ADC Sample Control
Starting a Sample Period

The “SAMP” bit in AD1CON1 starts and stops the

sample period
There are 2 ways to start a sample period:
Auto-start at the end of the previous conversion
Manually start by setting “SAMP”
ASAM
Auto start sample

Start and stop SAMP

End of conversion
sample control signal

Analog channel input ADC Digital output

VREF
ADC Control Register #1 (AD1CON1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRC2 SSRC1 SSRC0 ASAM SAMP

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 32

 ADC Sample Control
Stopping Sample Period & Starting Conversion
To stop a sample period and start a conversion, use the “SSRC”
bits in AD1CON1 to choose one of these options:
Manually stop by clearing the “SAMP” bit in ADxCON1
Timer3 or Timer5 timeout
Auto Sample timeout
External Interrupt pin Sample time = #TAD periods
PWM special event (SAMC<4:0> in AD1CON3)

SSRC<2:0>

Start and stop SAMP

sample control
Analog channel input ADC Digital output

VREF
ADC Control Register #1 (AD1CON1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRC2 SSRC1 SSRC0 ASAM SAMP

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 33

 ADC Channel Select
Connecting an Analog Pin to the ADC

Analog Channel 0 MUXA Input Select

Input Pins CH0SA3:CH0SA0 Sample & Hold
Amplifier
AN15
• VREFH VREFH
Voltage ref config •

MUX A
bits in AD1CON2 •
VCFG2:VCFG0
AN0
VREFL VREFL ADC
AN1
VREFH
AVSS

MUX B
VREF- Devices with 4
VREFL sample and holds
CH0NA/B have 4 channels
CH0 Negative
Input Select CH0SB3:CH0SB0 Channel 0 Select (Mux A):

Analog input circuits 1111: AN15

are device dependent.
0001: AN1
See data sheet.
0000: AN0

ADC Input Select Register (AD1CHS)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH0NB CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA CH0SA3 CH0SA2 CH0SA1 CH0SA0

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 34

 ADC Result Format Control

Result Buffer Format 10 bit Range 12 bit Range

MIN MAX MIN MAX
0000 00dd dddd dddd Unsigned Integer 0 1023 0 4095
ssss ssdd dddd dddd Signed Integer -512 511 -2048 2047
dddd dddd dd00 0000 Unsigned Fractional 0 0.999 0 0.9998
sddd dddd dd00 0000 Signed Fractional -1.0 .99804 -1.0 0.9995
ADCxBUF0
ADCxBUF0
• Controlled by the “Data
• •
• • Output Format” bits in
• •
• AD1CON1 (FORM1:FORM0)
ADCxBUF7

ADCxBUF8 Useful with DMA in

• Ping-Pong Mode
•
•
•
ADCxBUFF ADCxBUFF Controlled by the “Buffer Fill
Mode” bit in AD1CON2 (BUFM)
One 16 Result Buffer OR Two 8 Result Buffers
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 35
 ADC Channel Scanning
AN0 #1
AN32 AN1 #1
AN31 AN5 #1
• AN7 #1
• AN0 #2
•
32:1 Analog Mux

• AN1 #2
•
AN7 AN5 #2
AN7 #2
AN6
AN5 ADC AN0 #3
AN4 AN1 #3
AN3 VREF AN5 #3
AN2 AN7 #3
AN1 AN0 #4
AN0 Enable Channel AN1 #4
Scanning # Samples per AN5 #4
Interrupt (1 to 32) AN7 #4
ADC Control Register #2 (AD1CON2) ADC Result Buffer
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
CSNA SMPL4 SMPL3 SMPL2 SMPL1 SMPL0

Channel Scan Select Register (AD1CSSL)

15 14 13 12 11 10 9 8 AN7 6 AN5 4 3 2 AN1 AN0 Select channels for
CSS7 CSS5 CSS1 CSS0 automatic conversion

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 36

 ADC Channel Scanning
With DMA in Scatter/Gather Mode
AN0 #1
AN32
One DMA Channel AN0 #2
AN31 AN0 #3
• DMA Request AN0 #4
• AN1 #1
•
32:1 Analog Mux

• AN1 #2
•
AN7 AN1 #3
AN1 #4
AN6
AN5 ADC DMA AN5 #1
AN4 AN5 #2
AN3 VREF AN5 #3
AN2 AN5 #4
AN1 Peripheral Indirect AN7 #1
AN0 Address (PIA) AN7 #2
AN7 #3
AN7 #4
Data Memory
DMA uses info from ADC to
generate Data Memory addresses
Each channel has it’s own
buffer in Data Memory

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 37

 Calculating Minimum Sample Time
Example Calculation

The programmer must ensure the voltage

on the sample cap has reached its
maximum voltage during the sample time.
Sample Time
TSAMP = TAMP + TC + TCOFF
TAD

Sample Amplifier Sample Cap Temp

Time Settling Charge Time Coefficient VHOLD
Time

The following slides provide detailed

calculations for each term
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 38
 Calculating Minimum Sample Time
Amplifier Settling Time
16-bit devices have an ADC internal amplifier
settling time of about 0.5 µs.
This settling time is difficult to measure and is usually not
specified in the data sheet.
If external components are used to pre-condition the
analog signal, there may be an external amplifier
settling time to consider.
Since the external circuitry on the Explorer 16 is a
mechanical POT, this number is 0 µs.

TAMP = TAMP INT + TAMP EXT

Amplifier Internal Amplifier External Amplifier

Settling Time Settling Time Settling Time
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 39
 Calculating Minimum Sample Time
Sample Capacitor Charge Time

The source impedance RS (2.5k max) is the

only parameter the designer has control over
in determining charging time.

TC = - (CHOLD)(RIC + RSS + RS)ln(1/2048)s

Charge Sample Cap

Time Capacitance Interconnect Sample Switch Source
Resistance Resistance Impedance

RS ANx RIC RSS RS = 2.5K

RIC = 250
VA Analog Input Pin CHOLD
RSs = 3K
External Circuit CHOLD = 4.4pF
(Source Impedance)
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 40
 Calculating Minimum Sample Time
Temperature Coefficient

Temperatures above 25 degrees C will slow down

the time it takes to charge the sample capacitor
TCOFF = 0 at room temp and below

TCOFF = (Temp - 25°C)(0.005s/°C)

Temperature Operating
Coefficient Temperature (°C)

Maximum temps:
Industrial: 85°C
Extended: 125°C

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 41

 Calculating Minimum Sample Time
Example Calculation

Given these conditions:

External Amplifier Settling Time (TAMP EXT) = 0 µs
Source Impedance (RS) = 2.5k Ω
Temperature = 85° C
TAMP = TAMP INT + TAMP EXT = 0.5s

TC = - (CHOLD)(RIC + RSS + RS)ln(1/2048)s = 0.21s

TCOFF = (Temp - 25°C)(0.005s/°C) = 0.3s

TSAMP = TAMP + TC + TCOFF = 1.0s Minimum

Sample Time
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 42
 Lab 2:
Working with the Analog to Digital Converter
Peripheral Pin Select
PPS
 Peripheral Pin Select

What it is…
Pin multiplexing that allows user to select
the pin out of digital functions
Allows optimal usage of on-board
peripherals
Allows Pin Redefinition via software
What it is not …
Not a method to achieve pin compatibility
Analog and special pad pins (e.g., PMP &
I2C™) are still fixed

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 45

 Application example
Memory Serial Channels
64K Flash I2C™
8K RAM SPI x 2
Analog UART x 2
2 ch ADC
Vref +&-
Comparator x 2
Digital I/O
4 I/O

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 46

Application example
Application
64 KB Flash, 8 KB RAM
2 ch A/D, Ext. VREF
2 Comparators
UART x 2, I2C, SPI x 2
4 Digital I/O
Pin multiplexing blocks
functions
UART1 and SPI1
Comparator2 and SPI1
25 spare pins
Must use even larger pin
count device
Or write SPI in software

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 47

 Remappable Functions
All SPI & UART Functions
Timer & External Interrupt inputs
Input Captures & Output Compares
Analog Comparator outputs
PWM Fault input pins
Quadrature Encoder Interface inputs
Data Converter Interface
CAN
DSP Functions
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 48
 PPS Implementation Details

Any function can remap to any RP pin

Multiple functions on one pin are supported
Inputs vs. Outputs
Inputs assign a pin to a specific peripheral
Outputs assign a peripheral to a specific pin
Pinout is set in software
Allows on-the-fly configuration or one-shot
configuration

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 49

 Remappable Inputs
Peripheral Input
Pin Select Bits
Pad
RP0
Logic

RP1 Pad
Logic
Input to Peripheral
Pad
RP2
Logic

Pad
RPn
Logic

//C Example – Map U1RX to RP8

RPINR18bits.U1RXR = 8;

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 50

 Remappable Inputs

efine the location of each function used by modifying xxxxR bits in RPINRn registers

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 51

 Remappable Outputs

Peripheral Output
Select Bits

Peripheral 1 Output
Peripheral 2 Output

Peripheral 3 Output
Pad
RP0
Logic

Peripheral N Output

//C Example – Map U1TX to RP1

RPOR0bits.RP1R = 3

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 52

Remappable Outputs

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 53

 Remappable Outputs

efine the output functionality on each pin by modifying RPnR bits in RPORn registers
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 54
 PPS Register Protection
HW integrity checking
Bit flip will cause device reset
I/O lock feature
RPINRn/RPORn can only be written to, while
the IOLOCK bit in the OSCCON register = 0;
once the IOLOCK is set, the registers cannot be
written.
IOLOCK Protection
The state of the IOLOCK bit can only be
changed with an unlocking sequence
Protection selectable by configuration bit

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 55

 Pin Function Priority

Peripheral priorities:
1. Analog Functions ANx, Vref+/-
2. PPS Outputs UART TX, SDO, OC
3. PPS Inputs UART RX, SDI, IC
4. Fixed Digital Peripheral Outputs I2C, PMP
5. Fixed Digital Peripheral Inputs I2C, PMP

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 56

 Initializing a PPS Application
1. Design Decision: Static or Dynamic
RPn assignment?
 Set IOL1WAY config bit accordingly
2. Initialize the pinout by mapping the
RPn pins to the desired peripheral
input/output functions
 Map RPn pin(s)Peripheral Input Function(s)
 Map Peripheral Output Function(s)RPn
pin(s)
 Lock the RPn SFRs using ‘lock’ sequence
3. Configure Peripherals
4. Enable Interrupts (if required)

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 57

 Cool Byproducts
Increase drive strength by outputting same
peripheral on multiple pins

Peripheral Output Pad

Logic
e.g. OC1 RP1

Pad
Logic
RP2

Pad
Logic
RP3

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 58

 Cool Byproducts
Connect one signal to multiple peripheral inputs

Pad Input to Peripheral #1

RP0
Logic
e.g. U1CTS

Input to Peripheral #2
e.g. INT1

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 59

 Cool Byproducts
Connect peripheral output to another input
(Loopback) for debugging

Pad Input to Peripheral

RP0
Logic e.g. SDI

Output to Peripheral
e.g. SDO

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 60

 Application Example Revisited

Application
64 KB Flash, 8 KB RAM
2 ch A/D, Ext. VREF
2 Comparators
UART x 2, I2C, SPI x 2
4 Digital I/O

3 Spare Pins

Smaller packages, simplified design and lower cost!

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 61
Timers
 Timer Overview
Five or more 16-bit General Purpose
Timers/Counters
Similar functionality between all 5 timers
External crystal input for Timer1 only
Period Registers for Each
Interrupt generation & Timer Reset on match
Gated Timer can be used to measure the
duration of an external signal
When TGATE is high, Timer increments
When TGATE goes low, Timer stops and an interrupt
is generated
Four of these timers (Timer 2+3 and 4+5) can
make two 32-bit timers/counters

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 63

 Timers in 16-bit Mode
SOSC0/ TON TCKPS<1:0>
TxCK LP Sync
Sync
SOSC1 OSC Gate Prescaler
Prescaler
Gate
Sync
Sync 1,
1, 8,
8, 64,
64, 256
256

SOSCEN TCY TMR2

TMR2
TCS Reset
Timer1 ONLY
TGATE 16
16 bit
bit Comparator
Comparator
Equal

PR2
PR2
Period
Register ADC Event Trigger

Falling Set Timer3

Falling edge
edge
detect
detect Interrupt Flag
TGATE
TimerX Control Register (TxCON)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
TON TGATE TCKPS1 TCKPS0 T32 TCS

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 64

 Timers in 32-bit Mode
TON TCKPS<1:0>
TxCK Sync
Sync
Gate Prescaler
Prescaler
Gate
Sync
Sync 1,
1, 8,
8, 64,
64, 256
256

TCY TMR3
TMR3 TMR2
TMR2
TCS Reset
Timer2 & Timer3 and
Timer4 & Timer5 can be TGATE 32
32 bit
bit Comparator
Comparator
combined to work like Equal

one 32 bit timer PR3

PR3 PR2
PR2
Period
Control registers for Registers ADC Event Trigger
Timer3 and 5 are ignored
Falling Set Timer3
Falling edge
edge
detect
detect Interrupt Flag
TGATE
TimerX Control Register (TxCON)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
TON TGATE TCKPS1 TCKPS0 T32 TCS

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 65

 Lab 3:
Working with a 32-bit Timer
Input Capture
 Input Capture
Times the duration of an external event
Can be used for pulse, period, or duty cycle
measurement
Up to five Input Capture Channels T IM
E
Captures 16-bit timer value STA
M
Resolution of one instruction cycle
P
Timer2 or Timer3 as time base

2ND Timer Value – 1ST Timer Value

Pulse Width =
Timer Frequency
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 68
 Input Capture
Block Diagram (one of several types)
Prescaler
Prescaler Timer2 Timer3
ICx Edge
Edge detection
detection Timer2 Timer3
Counter
Counter logic
logic and
and Sync
Sync
(1,
(1, 4,
4, 16)
16)
Input
ICTMR
Capture Pin
Event
Event and
and
Set Input Capture
Interrupt
Interrupt Logic
Logic
Interrupt Flag

Input Capture Modes 4-Level

111: ICx pin functions as interrupt while in SLEEP or IDLE FIFO ICxBUF
ICxBUF
101: Capture on every sixteenth rising edge
100: Capture on every forth rising edge
011: Capture on every rising edge
010: Capture on every falling edge
001: Capture on every edge (both rising and falling)
000: Capture module is turned off
Input Capture #x Control Register (ICxCON)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICTMR ICI1 ICI0 ICM2 ICM1 ICM0

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 69

 Input Capture
Block Diagram (one of several types)
Prescaler
Prescaler Timer2 Timer3
ICx Edge
Edge detection
detection Timer2 Timer3
Counter
Counter logic
logic and
and Sync
Sync
(1,
(1, 4,
4, 16)
16)
ICTMR

Event
Event and
and
Set Input Capture
Interrupt
Interrupt Logic
Logic
Interrupt Flag

4-Level
Input Capture Interrupt Modes FIFO ICxBUF
ICxBUF
11: Interrupt on every fourth capture event
10: Interrupt on every third capture event
01: Interrupt on every second capture event
00: Interrupt on every capture event

Input Capture #x Control Register (ICxCON)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICTMR ICI1 ICI0 ICM2 ICM1 ICM0

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 70

 Output Compare &
Pulse Width Modulation (PWM)
 Output Compare & PWM
Changes an output pin and/or generates an
interrupt when a specific amount of time has
passed
Up to 8 Output Compare/PWM channels
0 to 100% duty cycle
Output Compare & PWM modes:
Set, Reset or Toggle pin What is PWM?
Duty Cycle is
Single pulse, Continuous pulse Modulated

Pulse Width Modulation (PWM)

OCx

Fixed Frequency
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 72
 Output Compare
Block Diagram (one of several types)
Output Compare Output Compare Output
Set Output Compare
Register Register Secondary Compare Pin
Interrupt Flag
OCxR
OCxR OCxRS
OCxRS
S
S Q
Q OCx
Output
Output
Comparator
Comparator R
R
Compare
Compare Logic
Logic

OCTSEL
OCFA or OCFB
OCM<2:0>
PWM Fault Pins
TMR2
TMR2 TMR3
TMR3
Output Compare Modes:
Comparator
Comparator Comparator
Comparator 11x: PWM
Period Register 10x: Single or continuous pulse
PR2
PR2 PR3
PR3 0xx: Set, Clear, or Toggle OCx Pin
Timer3 Output Compare
Timer2 See data sheet for details
Timer Select

Output Compare #x Control Register (OCxCON)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTSEL OCM2 OCM1 OCM0

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 73

 Output Compare
Single Pulse Mode
Output Compare Output Compare Output
Set Output Compare
Register Register Secondary Compare Pin
Interrupt Flag
OCxR
OCxR OCxRS
OCxRS
S
S Q
Q OCx
Output
Output
Comparator
Comparator R
R
Compare
Compare Logic
Logic

OCTSEL
OCM<2:0>
TMR2
TMR2 TMR3
TMR3

Comparator Comparator
PR2/3
PR2/3
Comparator Comparator
OCxR
OCxR OCxRS
OCxRS
PR2
PR2 PR3
PR3
Timer2 Timer3

OCx
TMR2/3 reset to 0
on period match TMR2/3

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 74

 Output Compare
Pulse Width Modulation (PWM) Mode
Double Buffered Duty Output
Cycle Registers Set Output Compare
Interrupt Flag Compare Pin
OCxR
OCxR OCxRS
OCxRS
S
S Q
Q OCx
Output
Output
Comparator
Comparator R
R
Compare
Compare Logic
Logic

OCTSEL
OCFA or OCFB
OCM<2:0>
PWM Fault Pins
TMR2
TMR2 TMR3
TMR3

At start of period:
Comparator Comparator OCxRS
OCxRS
Comparator Comparator  OCxRS copied
into OCxR
PR2
PR2 PR3
PR3  OCx set high OCxR
OCxR PR2/3
PR2/3
Timer2 Timer3

TMR2/3 reset to 0 OCx

on period match
TMR2/3

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 75

 Lab 4:
Generate a Pulse Width Modulated (PWM) Signal
 UART
Universal Asynchronous Receiver Transmitter
 UART Overview
Serial interface used for RS-232, RS-485, & LIN
Can also be used for chip to chip
communications and debug
4-deep FIFO for TX and RX buffers
Parity, Framing and Buffer Overrun Error Detect
Supported options:
9-bit mode (Address Detect)
Auto baud rate detect
TX
Loopback
Flow control RX
IrDA encoder/decoder
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 78
 UART TX Block Diagram
Write to 4-Level FIFO
this register
UART Enable UARTEN
UTXBF UxTXREG
TX Enable UTXEN UxTXREG is Full
Transmit
Transmit UxTXREG
Control
Control TRMT TSR is empty
9
Parity & 8 or 9 PDSEL1 Transmit
Transmit Shift
Shift
data bits select PDSEL0 Register Data
Register (TSR)
(TSR)

# of Stop Parity
STSEL Parity UxTX
bits select Baud
Baud Rate
Rate Parity Generator
Generator
High Baud Generator
Generator Start
BRGH 0
Rate select UART TX Pin
Stop
1
UARTx Mode Register (UxMODE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
UARTEN LPBACK BRGH PDSEL1 PDSEL0 STSEL

UARTx Status & Control Register (UxSTA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UTXEN UTXBF TRMT PERR FERR URXDA

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 79

 UART RX Block Diagram
URXDA Receive Data
Available

UART Enable UARTEN Read from 4-Level FIFO

this register Parity Error
Transmit
Transmit Framing Error
Control
Control UxRXREG
UxRXREG PERR
PERR FERR
FERR
Parity & 8 or 9 PDSEL1
9
data bits select PDSEL0 UxTX
Receive
Receive Shift
Shift
# of Stop Register
Register (RSR)
(RSR)
STSEL UxRX
bits select Baud
Baud Rate
Rate
High Baud Generator
Generator Parity
BRGH Parity Generator
Generator
Rate select LPBACK UART
RX Pin
UARTx Mode Register (UxMODE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
UARTEN LPBACK BRGH PDSEL1 PDSEL0 STSEL

UARTx Status & Control Register (UxSTA)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UTXEN UTXBF TRMT PERR FERR URXDA

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 80

 UART Baud Rate Generator
Instruction FFCY /4 or
CY/4 or 16-bit
16-bit Baud
Baud
F
Frequency CY FFCY /16
CY/16
Rate
Rate Timer
Timer
High Baud BRGH Comparator
Comparator Baud Clock
Rate select

UxBRG
UxBRG Baud Rate
Register
UART Baud Rate Generator

BRGH = 0 FCY
(standard Baud Rate =
16 x (UxBRG + 1)
speed)
See the UART section in
BRGH = 1 FCY the Family Reference
(high speed) Baud Rate = Manual for tables of baud
4 x (UxBRG + 1)
rates and BRGH settings
UARTx Mode Register (UxMODE)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UARTEN BRGH PDSEL1 PDSEL0 STSEL
© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 81
 Lab 5:
Working with the UART
 Questions?

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 83

Thank You!
 Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, KeeLoq, KeeLoq logo,
MPLAB, MPLAB X, PIC, PICmicro, PICSTART, PIC 32 logo, rfPIC and UNI/O are
registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
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and The Embedded Control Solutions Company are registered trademarks of
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dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE,
In‑Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo,
MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC,
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All other trademarks mentioned herein are property of their respective companies.

© 2011 Microchip Technology Incorporated, All Rights Reserved.

© 2012 Microchip Technology Incorporated. All Rights Reserved. Slide 85