Design

Design for
for Testability
Testability Theory
Theory and
and Practice
Practice

Lecture
Lecture 7:
7: Sequential
Sequential ATPG
ATPG
 Problem of sequential circuit ATPG
 Time-frame expansion
 Nine-valued logic
 ATPG implementation and drivability
 Complexity of ATPG
 Cycle-free and cyclic circuits
 Asynchronous circuits
 Summary

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 Sequential
Sequential Circuits
Circuits
 A sequential circuit has memory in addition to
combinational logic.
 Test for a fault in a sequential circuit is a
sequence of vectors, which
 Initializes the circuit to a known state
 Activates the fault, and
 Propagates the fault effect to a primary output
 Methods of sequential circuit ATPG
 Time-frame expansion methods
 Simulation-based methods

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 Example:
Example: A
A Serial
Serial Adder
Adder
An Bn
1 1
s-a-0
D
1

1 D
X
Cn
Cn+1
X
Combinational logic 1
Sn X
FF

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 Time-Frame
Time-Frame Expansion
Expansion
An-1 Bn-1 An B n
Time-frame -1 Time-frame 0
1 1 1
s-a-0 1
D X s-a-0
D D
1 1
Cn-1 1 D X D
Cn 1 1
Cn+1
X
1
Combinational logic Combinational logic 1
Sn-1 Sn
X
D

FF

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 Concept
Concept of
of Time-Frames
Time-Frames
 If the test sequence for a single stuck-at fault
contains n vectors,
 Replicate combinational logic block n times
 Place fault in each block
 Generate a test for the multiple stuck-at fault using
combinational ATPG with 9-valued logic
Vector – n +1 Vector – 1 Vector 0
Fault

Unknown Time- Time- Time-

State Next
or given Frame variables frame frame state
Init. state - n+1 -1 0
Comb.
block PO – n +1 PO – 1 PO 0
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Example
Example for
for Logic
Logic Systems
Systems

FF1
B

A FF2
s-a-1

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 Five-Valued
Five-Valued Logic
Logic (Roth)
(Roth)
0,1, D
0,1, D,, D
D,, X
X
A 0 A 0

s-a-1 s-a-1
D D
X X X
FF1 FF1

X D D
FF2 FF2

B X B X
Time-frame -1 Time-frame 0

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 Nine-Valued
Nine-Valued Logic
Logic (Muth)
(Muth)
0,1,
0,1, 1/0,
1/0, 0/1, 1/X,
0/1, 1/ 0/X
X, 0/ X,, X/ 0, X/
X/0, 1, X
X/1, X
A 0 A X

s-a-1 s-a-1
0/1 X/1
X 0/X 0/X
FF1 FF1

X 0/1 X/1
FF2 FF2

B X B 0/1
Time-frame -1 Time-frame 0

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 Implementation
Implementation of
of ATPG
ATPG
 Select a PO for fault detection based on drivability analysis.
 Place a logic value, 1/0 or 0/1, depending on fault type and
number of inversions.
 Justify the output value from PIs, considering all necessary
paths and adding backward time-frames.
 If justification is impossible, then use drivability to select
another PO and repeat justification.
 If the procedure fails for all reachable POs, then the fault is
untestable.
 If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can
be justified, the the fault is potentially detectable.

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 Drivability
Drivability Example
Example
(11, 16)
(10, 15) (22, 17)
(10, 16)
d(0/1) =

8
d(0/1) = 4 s-a-1
d(0/1) = d(1/0) = 32

8
d(1/0) =
8

(5, 9) d(1/0) = 20
(4, 4)
(17, 11)
(CC0, CC1) d(0/1) = 9 (6, 10)
FF d(0/1) = 120
d(1/0) =
8

= (6, 4) d(0/1) = 109 d(1/0) = 27

d(1/0) =

8
CC0 and CC1 are SCOAP combinational controllabilities

d(0/1) and d(1/0) of a line are effort measures for driving

a specific fault effect to that line

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 Complexity
Complexity of
of ATPG
ATPG
 Synchronous circuit -- All flip-flops controlled by clocks; PI and
PO synchronized with clock:
 Cycle-free circuit – No feedback among flip-flops: Test
generation for a fault needs no more than dseq + 1 time-
frames, where dseq is the sequential depth.
 Cyclic circuit – Contains feedback among flip-flops: May
need 9Nff time-frames, where Nff is the number of flip-
flops.
 Asynchronous circuit – Higher complexity!

Smax Time- Time- S3 Time- S2 Time- S1 Time- S0

Frame Frame Frame Frame Frame
max-1 max-2 -2 -1 0
max = Number of distinct vectors with 9-valued elements = 9Nff

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 Cycle-Free
Cycle-Free Circuits
Circuits

 Characterized by absence of cycles among flip-

flops and a sequential depth, dseq.
 dseq is the maximum number of flip-flops on any
path between PI and PO.
 Both good and faulty circuits are initializable.
 Test sequence length for a fault is bounded by
dseq + 1.

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 Cycle-Free
Cycle-Free Example
Example
Circuit

F2
2
All faults are
F3 testable in
F1 this circuit.
Level = 1 3
F2
2
s - graph
F1 F3 dseq = 3
Level = 1 3

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 Cyclic
Cyclic Circuit
Circuit Example
Example
Modulo-3 counter

Z
CNT F2
F1

s - graph

F1 F2

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 Modulo-3
Modulo-3 Counter
Counter
 Cyclic structure – Sequential depth is undefined.
 Circuit is not initializable. No tests can be
generated for any stuck-at fault.
 After expanding the circuit to 9Nff = 81, or fewer,
time-frames ATPG program calls any given target
fault untestable.
 Circuit can only be functionally tested by multiple
observations.
 Functional tests, when simulated, give no fault
coverage.

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Adding
Adding Initializing
Initializing Hardware
Hardware
Initializable modulo-3 counter

Z
CNT F2
F1
s-a-0

s-a-1
CLR
s-a-1 s-a-1 Untestable fault
Potentially detectable faults

s - graph
F1 F2

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 Benchmark
Benchmark Circuits
Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Seq. depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Abandoned faults 0 0 76 97
Fault coverage (%) 99.8 94.7 93.1 91.6
Fault efficiency (%) 100.0 100.0 94.8 93.4
Max. sequence length 3 3 24 28
Total test vectors 313 308 525 559
Gentest CPU s (Sparc 2) 10 15 19941 19183

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 Summary
Summary
 Combinational ATPG algorithms are extended:
 Time-frame expansion unrolls time as combinational array
 Nine-valued logic system
 Justification via backward time
 Cycle-free circuits:
 Require at most dseq + 1 time-frames
 Always initializable
 Cyclic circuits:
 May need 9Nff time-frames
 Circuit must be initializable
 Partial scan can make circuit cycle-free
 Asynchronous circuits: Not discussed
 See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000, Chapter 8.

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 Exercise
Exercise 3:
3: Lecture
Lecture 7
7
 Which type of circuit is easier to test? Circle one in each:
 Combinational or sequential
 Cyclic or cycle-free
 Synchronous or asynchronous

 What is the maximum number of input vectors that may be

needed to initialize a cycle-free circuit with k flip-flops?

Copyright 2001, Agraw Day-2 AM Lecture 7 19

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 Exercise
Exercise 3
3 Answers
Answers
 Which type of circuit is easier to test? Circle one in each:
 Combinational or sequential
 Cyclic or cycle-free
 Synchronous or asynchronous

 What is the maximum number of input vectors that may

be needed to initialize a cycle-free circuit with k flip-flops?

k vectors. Because that is the maximum sequential

depth possible. An example is a k bit shift register.

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