BUILD A SIMPLE COMPUTER

Lecturer: Pazir Ahmad

We know how to build digital circuits to
 store data (memory)
 do arithmetics (addition, multiplication)
 perform logic operations (negation, logic AND)
 control circuits (e.g. multiplexer)

How can we put these together to form a computer?

What is a computer?
WHAT IS A COMPUTER?
Definition (Digital Computer):
“A digital computer is a machine that can solve problems for people by
carrying out instructions given to it. A sequence of instructions describing how
to perform a certain task is called a program.”
– Tanenbaum: Structured Computer Organization

we have to “execute programs”, how can we achieve this?


store the program in memory
 execute its instructions step-by-step
VON NEUMANN ARCHITECTURE
 Modern computers are based on the von Neumann-Architecture (proposed by
John von Neumann in 1945)
 It describes how to build a stored program computer (program and data is kept in
memory)
A SIMPLE COMPUTER

 We will build a simple stored-program computer as an example

microarchitecture
 This is based upon ASC described in the book:

“Sajjan G. Shiva – Computer Design and Architecture” (p. 262 4th edition.)
 It is a 16-bit machine
ASC COMPONENTS
THE ASC ALU
 Processes 16-bit numbers in Two’s complement
 Supports addition (ADD), complementing (COMP)

, shifting (SHR,SHL)
 Can also transfer one of the two input buses

to the output (TRA1, TRA2)

 SHR copies the sign bit to the left-most position

(called an arithmetic shift)

MEMORY
 Uses 16 bit words
 Can address 216 = 64000 words (128000 bytes)
 Stores the data and the instructions
REGISTERS
 ASC uses 9 16-bit registers, each has a special purpose:
 Accumulator (ACC)
 stores intermediate results from the ALU
 Program Counter (PC)
 storesthe address of the next instruction to
be executed
 Processor Status Register (PSR)
 holds the current status of the processor
 (e.g. has an overflow occurred?)
REGISTERS 2
 Instruction Register (IR)
 holds the current instruction
 Memory Address Register (MAR)
 stores the address of the memory cell we want to access
 Memory Buffer Register (MBR)
 stores the data coming from or going to memory
 Index Registers 1 – 3 (Index1 – Index3)
 used for indexed addressing
CONTROL UNIT
 The Control Unit manages everything by sending control signals to all other
components, e.g.:
 to the ALU (ADD, SHR, . . . )
 to the memory (READ, WRITE)
 to the bus structure (e.g. ACC!Bus1,Bus3!MAR)
BUSES
 16-bit buses are used to connect the different ASC components
 Each component is connected to a bus via a controlled buffer

 The control unit must guarantee that two components don’t write to a bus at the
same time
CONNECTING
ASC-COMPONENTS
CONNECTING ASC-COMPONENTS 2
CONTROLLING THE DATA FLOW

 The control unit sends signals to the different parts of this architecture
 These control signals are indicated by red arrows in the diagram on the last slide

 They go to:

1. The ALU (TRA1,TRA2,ADD,COMP,SHR,SHL)

2. To the memory (READ,WRITE)
3. To the Bus Structure (e.g. ACC to Bus1)
4. (Input/Output)
 Giving these signals in the right order makes our computer “run”
REGISTER TRANSFER LANGUAGE (RTL)
 We need an easier way to describe which control signals are active
 We use a register transfer language that describes what’s going on

 An arrow indicates a transfer, the +-sign is an addition using the ALU

RTL
 The symbolic notation used to describe the microoperation transfers
among registers is called a register transfer language.
 A register transfer language is a system for expressing in symbolic
form the microoperation sequences among the registers of a digital
module.
 It is a convenient tool for describing the internal organization of digital
computers in concise and precise manner. It can also be used to
facilitate the design process of digital systems.
 Information transfer from one register to another is designated in
symbolic form by means of a replacement operator.
 The statement:R2 R1

R1 R2

 It designates a replacement of the content of R2 by the content of R1.

By definition, the content of the source register R1 does not change
after the transfer.
 Every statement written in a register transfer notation implies
a hardware construction for implementing the transfer.

The statement:
P:R2 R1

• P is control function.
• The other is
datapath(ALU) part
RTL EXAMPLES

R1

clk ld
R2
ld

 Assume the load of both registers are active, what will

happen in the positive edge of the clock.
SOME DEFINITIONS AND RULES IN RTL
 The RTL statement is called microoperation
 Microoperations(µop) are the operation which take one or many
registers ,or memory locations as its inputs , do some calculations
and store the result in one or many registers or memory location as
output.
 µops must complete in only one clock cycle.
 In RTL the order of writing a statement is not important
 All the operations are synchronous with the clock.
 All the operations are executed in parallel.
MEMORY TRANSFER
 The transfer of information from a memory word to the outside
environment is called a read operation. The transfer of new
information to be stored into the memory is called a write
operation.

Memory
MAR

 Read: MBR M[MAR] MBR

 Write: M[MAR] MBR !!
Note : Every statement written in a register transfer
notation implies a hardware construction for implementing
the transfer.
 Itmeans you should have a hardware construction for the
RTL statement you are writing.
ARITHMETIC MICROOPERATIONS
 What you think about the following RTL statement. Is it a
µop ?
 R1 R2×R3

 If there is a combinational circuit which can do the multiplication

in one clock cycle, then it is µop ,otherwise not.
EXAMPLES
 Write all the µop of the following circuit.

Cin

A
R1
X
B ALU R3
R2
S1S2
0 0 X=A
S1 S2 0 1 X=B
1 0 X=A+B
1 1 X=A+B+Cin
 Write all µop of the following circuit.
 Does the statement is valid in this circuit : TR PC+1
 Write the RTL statements to load 1 into TR.

 Write timing diagram for PC TR.

S0
BUS
S1

TR 1

LD

S1 S0 PC 2
0 1 TR into Bus LD INC CLR
1 0 PC into Bus

CLK
 If we have several RTL statements , they execute in parallel.
How to make them sequential?
 PC 0
 PC PC+1
 What would be the value of PC ?

 We can bring order using sequence counter.

 In the sequence counter you have counter which count up in
every pulse of clock.

T0:PC 0
T0 T1:PC PC+1
.
Seq 3×8 .
counter Decoder .
.
.
T7
CLK
How does ASC work?
INSTRUCTION CYCLE
 To execute a program the Control Unit has to:
1. Fetch: Load the current instruction specified by the PC from memory to the IR
2. Decode: Interpret the contents in the Instruction Register (IR)
3. Execute: Execute the specified Instruction
4. go back to 1
 To start this cycle the PC has to be loaded with a special address when the computer is
switched on
FETCH IN RTL
 We can describe how to fetch the instruction in RTL:

 Let’s see what happens here in detail. . .

1. FETCHING AN INSTRUCTION
Details

 PC (Program Counter) to Bus1

 TRA1-signal to ALU

 Bus3 to MAR (Memory Address

Register)
 send READ command to memory

 Result: MAR PC; READ

2. FETCHING AN INSTRUCTION
3. FETCHING AN INSTRUCTION
THE COMPLETE FETCH CYCLE
THE DECODE CYCLE
 The contents of the IR are decoded by the control unit.
 How this decoding works depends on the instruction format.

 before we can continue we have to define it first!

 How is instruction format
ASC INSTRUCTION FORMAT

 Bit 11-15: Opcode (5 bit)

 Bit 10: Indirect flag (1 bit)
 Bit 8-9: Index flag (2 bits)
 Bit 0-7: Address (8 bits)
 e.g.: the instruction 0011000010110111 means: use operation 110 on address
10110111 using no indexing and direct addressing.
ZERO-ADDRESS INSTRUCTIONS

 A zero address instruction consists of only the opcode

 The rest of the instruction word is not needed.
ONE-ADDRESS INSTRUCTIONS

 We now use the complete instruction word

 So what do indirect and index flags mean?

 Sometimes the symbolic address (given in the instruction) is not equal to the
effective address
 we explain this by looking at an example instruction:
 An example of one-address-instruction
LDA WITH DIRECT ADDRESSING

• Load the content of memory address bit 0-7 into ACC

• indirect flag=0 , index flag = 00
• the symbolic address is equal to the effective address
EXAMPLE: LDA DIRECT
LDA WITH INDEXED ADDRESSING

 bit 0-7 are the symbolic address m

 bit 8-9 give the number of the index register idx (!=0)
 the effective address is m + Indexidx
EXAMPLE: LDA INDEXED
LDA WITH INDIRECT ADRESSING

 bit 0-7 are the symbolic address m

 bit 10 (indirect flag) is 1
 the effective address is the value in memory cell m
EXAMPLE: LDA INDIRECT
LDA WITH INDEXED INDIRECT ADDRESSING

 We now combine indirection and indexing

 this means: the indirect flag is 1 and an index is given
 two ways to interpret this:
 pre-index: first perform indexing, then indirection
 post-index: first indirection, the indexing

 ASC will only support pre-indexed-indirect addressing

EXAMPLE: LDA PRE-INDEXED INDIRECT
SUMMARY: ADDRESSING MODES

 the four addressing modes ASC supports:

1. direct: e.g. LDA 0002
2. indexed: e.g. LDA 0001,2
3. indirect: e.g. LDA* 0002
4. pre-indexed indirect: e.g. LDA* 0001,2
 These can be used with every one-address instruction
MORE ONE-ADDRESS INSTRUCTIONS 1

Note: MEM is the given address, its contents are M[MEM]

MORE ONE-ADDRESS INSTRUCTIONS 2
 Instructions Accessing Index Registers

 These one-address instructions refer to index registers implicitly

 Indexed addressing therefore can’t be used with them
OPCODES

 We have 5 bits for the opcode

 for 14 instructions 4 are enough, so bit 11 is not used
THE CONTROL UNIT’S TASKS
 The control unit is a sequential circuit: outputs depend on internal state and
inputs.
 It has to generate the right signals at the right time.

 we can accomplish this with

 flip-flops
(to save the state)
 combinational circuitry (to generate the correct signals)

 This approach is called: hardwired control unit.

THE CONTROL UNIT’S TASKS
CONNECTING THE CONTROL UNIT
 Inputs to the CU
1. The current Instruction (16bit)
2. The PSR flags (5 bits)
3. A flag indicating if the current Index is 0
4. Start/Reset button, clock signal
 Outputs of the CU: all the control signals
 Internal State
INPUTS INTERNAL SIGNALS
OUTPUTS :
OUTPUT SIGNALS:
THE PROCESSOR STATUS REGISTER

 The PSR holds the current state of the processor

 its 5 flags indicate:
C (carry): carry occurred in ALU
 N (negative): contents of ACC are negative
 Z (zero): contents of ACC are 0
 O (overflow): overflow occurred in ALU
 I (interrupt): interrupt needs to be served
HARDWIRED CONTROL UNIT
 One instruction cycle consists of three phases
1. Fetch: Get the instruction, perform address calculation (indexing)
2. Defer: perform indirection
3. Execute: depending on the opcode
 Each phase consists of 4 subcycles

 One subcycle has the duration of the longest register transfer time
THE FETCH PHASE
 Fetching the instruction (3 subcycles):

 Performing Indexing (1 subcycle):

Remarks
 Note that we have to be able to put the address part of IR on Bus1

 Indexing is not performed when IR 15 = 1

 The reason: instructions accessing index registers (e.g. LDX)

(1) the symbol || is the concatenation operator
THE DEFER PHASE
 The defer phase is entered only when the indirect flag is set
 it comes after fetch. Therefore, the address (indexed if needed) is already in MAR

 we use the following time allocation:

Remarks
 We have to wait one subcycle for the memory to be read

 We used four subcycles because fetch also needed four.

 this is inefficient but makes the control unit easier to design.

THE EXECUTE PHASE
 Different for each instruction
 Also uses 4 subcycles for simplicity

Example: LDA
INSTRUCTION TYPES IN A SIMPLE COMPUTER(ASC)
1. Arithmetic Instructions(ADD, TCA)
2. Shift/Rotate Instructions (SHR and SHL)
3. Data Movement Instructions.(LDX,STX,LDA,STA)
4. Input/output Instructions(RWD,WWD)
5. Control Instructions(BRU,BIN,BIP, HLT, TDX , and TIX .)

Note :Logic Instructions(we don’t have in ASC)

ANALYSIS OF DATA FLOW DURING EXECUTION
ANALYSIS OF DATA FLOW DURING EXECUTION
(CONT.)
IMPLEMENTING THE HWCU
 We have defined how the hardwired CU should behave
 we will implement it using the following structure:
STATE TRANSITIONS
 In subcycle 4, we change the state to the next one.
 If bit 10 of IR is 0 we can skip the defer phase.

 Three instructions need only one register transfer: HLT, SHL, SHR

 they can be completed in one subcycle

 As they need no addressing we can execute them in subcycle 4 of the Fetch

phase
STATE TRANSITION LOGIC
 if IR10 = 1 we go from fetch to
defer, otherwise to execute
 if the operation is SHL, SHR or
HLT we stay in fetch state
EXAMPLE TIMING
 We can now examine the intended behavior over time
 Using the clock, we generate 4 subcycle signals

 Hardwired Control Unit Timing Diagram

STATE CIRCUITRY
 We can now implement the state circuitry of our CU
 States are encoded as follows:
 00: fetch
 01: defer Figure. State Circuit Diagram
 10: execute
A 4-PHASE CLOCK
A 4-PHASE CLOCK
 Each state (F,D,E) consists of 4 subcycles (T1 to T4)
 While running, a 4-phase clock generates the subcycle signals in order.
 A run-flip flop stores if the CU is running.
OPCODE DECODER
OPCODE DECODER
 We want one signal for each operation
 This is achieved by decoding the opcode contained in the IR
CONTROL SIGNAL GENERATION
CONTROL SIGNAL GENERATION
 For each state, subcycle and operation the CU has to output the correct signals
 This results in a huge but very simple circuit (basically only AND-gates)
FINISHING THE HWCU
 We have almost finished our HWCU for ASC, now:
1. write down which register transfers should occur when for each instruction
2. convert this to a combinational circuit
3. simplify the circuit when possible
4. put all the parts (clock, state, signal circuits) together