Sri.S.A.Hariprasad SR - Lecturer R.V.C.E Bangalore
Sri.S.A.Hariprasad SR - Lecturer R.V.C.E Bangalore
Sri.S.A.Hariprasad
Sr.Lecturer
R.V.C.E Bangalore
PERFORMANCE EQUATION
N ×S
T= R
N - Number of instruction (m/c)
S ± Average steps required to execute one machine instruction
R- Clock frequency
PERFORMANCE IMPROVEMENT
] Cache memory
]Pipelining
]Superscalar execution
CACHE MEMORY
] Cache can be built within the processor ± L1 cache
]Cache can be placed between main memory and CPU ± L2 Cache
]Cache size being small, currently required instructions and data for
execution are stored in cache
]Entire instructions and data connected with program cannot be stored
at a time, if program is big
]New set of programs (instructions and data) can be loaded by
swapping the previous contents back into memory
] Cache Hit ± If wanted item by CPU (instruction or data) is
present in cache.
]Cache miss ± If wanted item by CPU is not present in cache
]To improve the performance hit ratio to be increased
PIPELINING
T1 T2 T3 T4 T5 T6 T7 T8
F D E E
MOV R4,R5
Clk cycles 1 2 3 4 5
PERFORMANCE MEASURMENT
1/ 2
r
SPEC rating = J
1
MULTIPROCESSOR AND
MULTICOMPUTERS
MULTIPROCESSOR SYSTEM: System which
uses more than one processor unit.
]S.>1, N small
]Support to HLL
]N >>1, S is small
]Supports pipelining
DISADVANTAGES OF RISC
]RISC programs are longer than CISC program