Lecture 6:

Logical
Effort
 Outline
 Logical Effort
 Delay in a Logic Gate
 Multistage Logic Networks
 Choosing the Best Number of Stages
 Example
 Summary

6: Logical Effort CMOS VLSI Design 4th Ed. 2

 Introduction
 Chip designers face a bewildering array of choices
– What is the best circuit topology for a function?
– How many stages of logic give least delay?
???
– How wide should the transistors be?

 Logical effort is a method to make these decisions

– Uses a simple model of delay
– Allows back-of-the-envelope calculations
– Helps make rapid comparisons between alternatives
– Emphasizes remarkable symmetries

6: Logical Effort CMOS VLSI Design 4th Ed. 3

 Example
 Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file. A[3:0] A[3:0]
32 bits

4:16 Decoder
 Decoder specifications:

16 words
16
Register File
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
 Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?

6: Logical Effort CMOS VLSI Design 4th Ed. 4

 Delay in a Logic Gate
 Express delays in process-independent unit d  d abs
 Delay has two components: d = f + p 
3RC
 f: effort delay = gh (a.k.a. stage effort)
 3 ps in 65 nm process
– Again has two components
60 ps in 0.6 m process
 g: logical effort
– Measures relative ability of gate to deliver current
– g  1 for inverter
 h: electrical effort = Cout / Cin
– Ratio of output to input capacitance
– Sometimes called fanout
 p: parasitic delay
– Represents delay of gate driving no load
– Set by internal parasitic capacitance

6: Logical Effort CMOS VLSI Design 4th Ed. 5

 Delay Plots
d =f+p 2-input
= gh + p 6
NAND Inverter
g = 4/3

Normalized Delay: d
5 p=2
 What about d = (4/3)h + 2
4 g=1
NOR2? p=1
3 d=h+1

2 Effort Delay: f

1
Parasitic Delay: p
0
0 1 2 3 4 5

Electrical Effort:
h = Cout / Cin

6: Logical Effort CMOS VLSI Design 4th Ed. 6

Computing Logical Effort
 DEF: Logical effort is the ratio of the input
capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
 Measure from delay vs. fanout plots
 Or estimate by counting transistor widths
2 2 A 4
Y
2 B 4
A 2
A Y Y
1 B 2 1 1

Cin = 3 Cin = 4 Cin = 5

g = 3/3 g = 4/3 g = 5/3

6: Logical Effort CMOS VLSI Design 4th Ed. 7

 Catalog of Gates
 Logical effort of common gates

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

6: Logical Effort CMOS VLSI Design 4th Ed. 8

 Catalog of Gates
 Parasitic delay of common gates
– In multiples of pinv (1)
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8

6: Logical Effort CMOS VLSI Design 4th Ed. 9

Example: Ring Oscillator
 Estimate the frequency of an N-stage ring oscillator

Logical Effort: g=1 31 stage ring oscillator in

0.6 m process has
Electrical Effort: h=1 frequency of ~ 200 MHz
Parasitic Delay: p=1
Stage Delay: d=2
Frequency: fosc = 1/(2*N*d) = 1/4N

6: Logical Effort CMOS VLSI Design 4th Ed. 10

 Example: FO4 Inverter
 Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g=1

Electrical Effort: h=4 The FO4 delay is about

Parasitic Delay: p=1 300 ps in 0.6 m process

Stage Delay: d=5 15 ps in a 65 nm process

6: Logical Effort CMOS VLSI Design 4th Ed. 11

Multistage Logic Networks
 Logical effort generalizes to multistage networks
 Path Logical Effort G gi 
Cout-path
 Path Electrical Effort H
Cin-path
 Path Effort F   f i   gi hi

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

6: Logical Effort CMOS VLSI Design 4th Ed. 12

Multistage Logic Networks
 Logical effort generalizes to multistage networks
 Path Logical Effort G 
gi
Cout  path
 Path Electrical Effort H
Cin  path
 Path Effort F   f i   gi hi

 Can we write F = GH?

6: Logical Effort CMOS VLSI Design 4th Ed. 13

 Paths that Branch
 No! Consider paths that branch:
15
G =1 90
5
H = 90 / 5 = 18
GH = 18 15
90
h1 = (15 +15) / 5 = 6
h2 = 90 / 15 = 6
F = g1g2h1h2 = 36 = 2GH

6: Logical Effort CMOS VLSI Design 4th Ed. 14

 Branching Effort
 Introduce branching effort
– Accounts for branching between stages in path
Con path  Coff path
b
Con path
B   bi
Note:

h i  BH
 Now we compute the path effort
– F = GBH

6: Logical Effort CMOS VLSI Design 4th Ed. 15

 Multistage Delays
 Path Effort Delay DF   f i

 Path Parasitic Delay P   pi

 Path Delay D   d i  DF  P

6: Logical Effort CMOS VLSI Design 4th Ed. 16

 Designing Fast Circuits
D   d i  DF  P
 Delay is smallest when each stage bears same effort

fˆ  gi hi  F
1
N

 Thus minimum delay of N stage path is

1
D  NF  P N

 This is a key result of logical effort

– Find fastest possible delay
– Doesn’t require calculating gate sizes
6: Logical Effort CMOS VLSI Design 4th Ed. 17
 Gate Sizes
 How wide should the gates be for least delay?

ˆf  gh  g Cout
Cin

gi Couti
 Cini 
fˆ
 Working backward, apply capacitance
transformation to find input capacitance of each gate
given load it drives.
 Check work by verifying input cap spec is met.

6: Logical Effort CMOS VLSI Design 4th Ed. 18

 Example: 3-stage path
 Select gate sizes x and y for least delay from A to B

y
x
45
A 8
x
y B
45

6: Logical Effort CMOS VLSI Design 4th Ed. 19

 Example: 3-stage path
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ  3 F  5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

6: Logical Effort CMOS VLSI Design 4th Ed. 20

 Example: 3-stage path
 Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

y
x
45
45
A P:
84 P:
x 4
N: 4 P:
y 12 B
B
N: 6 45
N: 3 45

6: Logical Effort CMOS VLSI Design 4th Ed. 21

 Best Number of Stages
 How many stages should a path use?
– Minimizing number of stages is not always fastest
 Example: drive 64-bit datapath with unit inverter
Initial Driver 1 1 1 1

8 4 2.8

D = NF1/N + P 16 8

= N(64)1/N + N
23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

6: Logical Effort CMOS VLSI Design 4th Ed. 22

 Derivation
 Consider adding inverters to end of path
– How many give least delay? N - n1 ExtraInverters
Logic Block:
n1 n1Stages

D  NF   pi   N  n1  pinv
1
N Path Effort F

i 1
D 1 1 1
  F N ln F N  F N  pinv  0
N
1
 Define best stage effort F N

pinv    1  ln    0

6: Logical Effort CMOS VLSI Design 4th Ed. 23

 Best Stage Effort
 pinv    1  ln    0 has no closed-form solution

 Neglecting parasitics (pinv = 0), we find  = 2.718 (e)

 For pinv = 1, solve numerically for  = 3.59

6: Logical Effort CMOS VLSI Design 4th Ed. 24

 Sensitivity Analysis
 How sensitive is delay to using exactly the best
number of stages? 1.6
1.51

D(N) /D(N)
1.4
1.26
1.2 1.15

1.0

(=6) ( =2.4)

0.0
0.5 0.7 1.0 1.4 2.0

N/ N

 2.4 <  < 6 gives delay within 15% of optimal

– We can be sloppy!
– I like  = 4

6: Logical Effort CMOS VLSI Design 4th Ed. 25

 Example, Revisited
 Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the
decoder for a register file. A[3:0] A[3:0]
32 bits

4:16 Decoder
 Decoder specifications:

16 words
16
Register File
– 16 word register file
– Each word is 32 bits wide
– Each bit presents load of 3 unit-sized transistors
– True and complementary address inputs A[3:0]
– Each input may drive 10 unit-sized transistors
 Ben needs to decide:
– How many stages to use?
– How large should each gate be?
– How fast can decoder operate?

6: Logical Effort CMOS VLSI Design 4th Ed. 26

 Number of Stages
 Decoder effort is mainly electrical and branching
Electrical Effort: H = (32*3) / 10 = 9.6
Branching Effort: B=8

 If we neglect logical effort (assume G = 1)

Path Effort: F = GBH = 76.8

Number of Stages: N = log4F = 3.1

 Try a 3-stage design

6: Logical Effort CMOS VLSI Design 4th Ed. 27

 Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
Path Effort: F = GBH = 154
Stage Effort: fˆ  F 1/ 3  5.36
Path Delay: D  3 fˆ  1  4  1  22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]

10 10 10 10 10 10 10 10

y z word[0]

96 units of wordline capacitance

y z word[15]

6: Logical Effort CMOS VLSI Design 4th Ed. 28

 Comparison
 Compare many alternatives with a spreadsheet
 D = N(76.8 G)1/N + P
Design N G P D
NOR4 1 3 4 234
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

6: Logical Effort CMOS VLSI Design 4th Ed. 29

 Review of Definitions
Term Stage Path
number of stages 1 N
logical effort g G   gi
Cout-path
electrical effort h Cout
Cin
H Cin-path
Con-path Coff-path
branching effort b Con-path B   bi
effort f  gh F  GBH

effort delay f DF   f i

parasitic delay p P   pi
delay d f p D   d i  DF  P

6: Logical Effort CMOS VLSI Design 4th Ed. 30

 Method of Logical Effort
1) Compute path effort F  GBH
2) Estimate best number of stages N  log 4 F
3) Sketch path with N stages
1
4) Estimate least delay D  NF  PN

5) Determine best stage effort ˆf  F N1

gi Couti
6) Find gate sizes Cini 
fˆ

6: Logical Effort CMOS VLSI Design 4th Ed. 31

 Limits of Logical Effort
 Chicken and egg problem
– Need path to compute G
– But don’t know number of stages without G
 Simplistic delay model
– Neglects input rise time effects
 Interconnect
– Iteration required in designs with wire
 Maximum speed only
– Not minimum area/power for constrained delay

6: Logical Effort CMOS VLSI Design 4th Ed. 32

 Summary
 Logical effort is useful for thinking of delay in circuits
– Numeric logical effort characterizes gates
– NANDs are faster than NORs in CMOS
– Paths are fastest when effort delays are ~4
– Path delay is weakly sensitive to stages, sizes
– But using fewer stages doesn’t mean faster paths
– Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
 Provides language for discussing fast circuits
– But requires practice to master

6: Logical Effort CMOS VLSI Design 4th Ed. 33

 Practice 1

6: Logical Effort CMOS VLSI Design 4th Ed. 34

 Practice 2

6: Logical Effort CMOS VLSI Design 4th Ed. 35

 Practice 2

6: Logical Effort CMOS VLSI Design 4th Ed. 36

 Review
1. What are tpdr, tpdf, tf, tr, tcdr, tcdf?
2. Calculate arrive time of the following circuit:

20
10 40
30 40
3. Explain the delay estimation of a fanout-of-1 inverter (slide 10)
4. Explain the tpdr and tpdf delay estimation of 3-input NAND driving h
identical gates (slide 15).
5. Estimate delay for the gates: AOI21, OAI31
6. What is logical effort?
7. What is parasitic delay?
8. Estimate the delay of the following gate:

5: DC and Transient Response CMOS VLSI Design 4th Ed. 37