Unit-3 8085 Microprocessor

Microprocessor and Interfacing
Unit-3
8085 Microprocessor
Prof. Swati R. Sharma

[email protected]
Introduction to 8085
Microprocesssor
2
Unit-3
Unit-3 8085
8085 Microprocessor
Microprocessor 2 Darshan
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 8085 is pronounced as "eighty-eighty-five" microprocessor.
 It is an 8-bit microprocessor designed by Intel in 1977.
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 8-bit data bus.
 It is a single chip N MOS device with 40 pins.
 It has multiplexed address and data bus.(AD0 - AD7).
 It works on 5-Volt DC power supply.
 The maximum clock frequency is 3MHz while minimum frequency
is 500kHz.
 It provides 16 address lines, therefore capable of addressing
216= 65536 ≈ 64K of addressable memory.
 It supports external interrupt request.
 It has two 16 bit registers named program counters (PC) and stack
pointer (SP).
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 It generates 8 bit I/O address so it can access 28 = 256 input ports.
 It provides 5 hardware interrupts:
1. TRAP
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. INTR
 It provides accumulator, 5 flag register, 6 general purpose registers
and 2 special purpose registers (SP-Stack Pointer, PC-Program
Counter).
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Unit-3 8085
8085 Microprocessor
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8085 Programming Model
6
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Unit-3 8085
8085 Microprocessor
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General Purpose Registers

Accumulator A (8) Flag Register
B (8) C (8)
D (8) E (8)
H (8) L (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
Data Bus Address Bus
16
8
Bidirectional Unidirectional
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Unit-3 8085
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General Purpose Registers
B (8) C (8)
D (8) E (8)
H (8) L (8)
 6 general purpose registers to store 8-bit data B, C, D, E, H & L.

 Can be combined as fixed register pairs – BC, DE, HL to perform
16 bit operations.
 Used to store or copy data using data copy instructions.
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Unit-3 8085
8085 Microprocessor
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8
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Accumulator
 8-bit register, identified as A
 Part of ALU
 Used to store 8-bit data to perform arithmetic & logical
operations.
 Result of operation is stored in Accumulator A (8)
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8
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Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
S Z  AC  P  CY
P -Parity Flag
Set (1) if result has even no. of 1’s &
S -Sign Flag Reset(0) if result has odd no. of 1’s
:Undefined
Set (1) if 7th bit of result is 1;
AC -Auxiliary
1 0 0 Carry
1 0 0Flag1 1 CY -Carry Flag
otherwise reset (0)
1 0 1 0 1 0 1 0 Set (1) Pwhen
= 1 carry bit is Set (1) if arithmetic
Z -Zero Flag S = 1 generated by 3rd bit & operation results in
Set (1) when result is zero; passed to bit 4th bit. carry;
otherwise reset(0) otherwise reset(0)
1 1 1 1 1 1
1 0 1 0 0 0 1 0 11001100 1 0 1 0
-1 0 1 0 + 0 1 1 0+ 10010110 1 0 0 1
0 0 0 0 1 0 0 11 00001011 0 0 1 1
Z=1 AC = 1 CY = 1
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Unit-3 8085
8085 Microprocessor
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Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
S Z  AC  P  CY
 5 Flag Register for set/reset operations.

 Helpful in decision making.
 Conditions are tested through software instructions.
Example:
JC (Jump On Carry) is implemented to change the sequence of
program when CY(Carry Flag) is set(1).
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Unit-3 8085
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8
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Stack Pointer
Stack Pointer(SP)
 Used as memory pointer.
 Points to the memory location in
R/W memory called Stack.
 Beginning of stack is defined by
loading a 16-bit address in the
stack pointer.
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B (8) C (8)
D (8) E (8)
H (8) L (8)
16
8
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Stack Pointer & Program Counter
Program Counter(PC)
 Sequence the execution of an instructions.
CPU
Address Memory
PC 0003H Instruction 4
0002H
0002H Instruction 3
0001H Instruction 2
IR 0001H Instruction 2
0000H Instruction 1
0000H Instruction 1
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Bus Organization of 8085
18
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System bus
CPU Memory Input/Output
Control Bus
Address Bus
Data Bus
System Bus
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A15
Address Bus
A0
Memory Input
8085 MPU Output Real

World
D7
Data Bus
D0
Control Bus
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Unit-3 8085
8085 Microprocessor
Microprocessor Darshan
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Address Bus
 Group of 16 unidirectional lines generally identified as A0 to A15.
i.e. bits flow from microprocessor to peripheral devices.
 16 address lines are capable of addressing 65536 memory
locations. So, 8085 has 64K memory locations.
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Unit-3 8085
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A15
Address Bus
A0
Memory Input

World
D7
Data Bus
D0
Control Bus
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Data Bus
 Group of 8 lines identified as D0 to D7.
 They are bidirectional i.e. data flow in both directions between
microprocessor, memory & peripheral.
 8 data lines enable microprocessor to manipulate data ranging
from 00H to FFH (28=256 numbers).
 Largest number appear on data bus is 1111 1111 => (255)10.
 As Data bus is of 8-bit, 8085 is known as 8-bit Microprocessor.
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Unit-3 8085
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A15
Address Bus
A0
Memory Input

World
D7
Data Bus
D0
Control Bus
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Control Bus
 It comprises of various single lines that carry synchronization,
timing & control signals.
 These signals are used to identify a device type with which MPU
intends to communicate.
 Some control signals are Read, Write and Opcode fetch etc.
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8085 pin diagram
26
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Unit-3 8085
8085 Microprocessor
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• 8-bit general purpose
microprocessor.
• Capable of addressing 64K
of memory.
8085 pin diagram
• It has 40 pins.
• Requires +5V single power
supply.
28
8085 pin diagram
Signals are classified into 6 groups:
1. Address bus
2. Multiplexed address/data bus
3. Control & status signals
4. Power supply & frequency signals
5. Externally initiated signals
6. Serial I/O ports
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8085 pin diagram: Address Bus
 16 signal lines are used as address
bus.
 However these lines are split into
two segments: A15 - A8 and AD7 - AD0
 A15 - A8 are unidirectional and used to
carry high-order address of 16-bit
address.
 AD7 - AD0 are used for dual purpose.
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8085 pin diagram: Multiplexed Address/Data Bus
 Signal lines AD7-AD0 are
bidirectional and serve dual
purpose.
 They are used as low-order address
bus as well as data bus.
 The low-order address bus can be
separate from these signals by
using a latch (ALE).
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8085 pin diagram: Control & Status Signals
To identify nature of operation
 Two Control Signals
1. RD(Read)
2. WR(Write)
 Three Status Signals
1. S1
2. S0
3. IO/M
 To indicate beginning of operation
1. ALE(Address Latch Enable)
ALE  1, then Address bus
ALE  0, then Data bus
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ALE: Pin 30
 This is positive going pulse
generated every time the 8085
begins an operation (machine
cycle).
 It indicates that the bits on AD7-AD0
are address bits.
 This signal is used primarily to latch
the low-address from multiplexed
bus & generate a separate set of
address lines A7-A0.
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RD(Read): Pin 32
 This is a read control signal (active
low)
 This signal indicates that the
selected I/O or Memory device is
to be read & data is available on
data bus.
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WR (Write): Pin 31
 This is a write control signal (active
low)
 This signal indicates that the
selected I/O or Memory device is
to be write & data is available on
data bus.
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IO/M: Pin 34
 This is a status signal used to
differentiate I/O and memory
operation.
 When signal is
high  I/O operation
low  Memory operation
 This signal is combined with RD and
WR to generate I/O & memory
control signals.
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S1 (Pin 33) & S0 (Pin 29)
 These status signals can identify
various operations.
S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
1 1 OPCODE FETCH
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8085 pin diagram
I0/M RD WR Operation
0 0 0 HLT
0 0 1 MEMR
0 1 0 MEMW
0 1 1 Opcode
Fetch
1 0 0 HLT
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
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8085 Pin Diagram: Power Supply & Frequency Signal
 Vcc  Pin 40, +5V Supply.
 Vss  Pin 20, Ground Reference
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 X1, X2  Pin 1 & 2, Crystal
Oscillator is connected at these
two pins.
 The frequency is internally divided
by two;
therefore, to operate a system at
3MHz, the crystal oscillator should
have a frequency of 6MHz.
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 CLK (OUT)  Clock output
 Pin 37: This signal is used as system
clock for other I/O devices for
synchronization with Microprocessor.
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8085 Pin Diagram: Externally Initiated Signals
 INTR(Input)  Interrupt Request
It is used for general purpose
interrupt.
 INTA(Output)  Interrupt
Acknowledge.
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 RST7.5, RST6.5, RST5.5 (Input) 
Restart Interrupts.
 These are vector interrupts that
transfer the program control to
specific memory locations.
 RST7.5, RST6.5, RST5.5 have higher
priorities than INTR interrupt.
 Among these 3 interrupts, the
priority order (higher to lower) is
RST7.5, RST6.5, RST5.5
respectively.
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 TRAP(Input)  This is a non
maskable interrupt & has the
highest priority.
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 HOLD(Input)  This signal indicates
that a peripheral such as DMA
Controller is requesting the use of
address & data buses.
 HLDA(Output)  Hold Acknowledge
This signal acknowledges the HOLD
request.
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 READY(Input)  This signal is used
to delay the microprocessor read or
write cycles until low-responding
peripheral is ready to send or accept
data.
 When the signal goes low, the
microprocessor waits for an integral
no. of clock cycles until READY signal
goes high.
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 RESET IN (Input)  When the
signal on this pin goes low, the
Program Counter is set to zero,
the buses are tri-stated &
microprocessor is reset.
 RESET OUT (Output)  This
signal indicates that
microprocessor is being reset. The
signal is also used to reset other
devices.
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8085 Pin Diagram: Serial I/O Ports
Two pins for serial transmission
1. SID (Serial Input Data)
2. SOD (Serial Output Data)
 In serial transmission, data bits
are sent over a single line, one bit
at a time.
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8085 pin diagram
49
8085 Architecture/Block Diagram
8 5
80
50
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INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD
Interrupt Control Serial I/O Control
8-Bit Internal Data Bus
Instructio
Accumulator (8) Temp. Reg. (8) Multiplexer
n Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder Reg. Reg.
Register Select
Flag (5) and D (8) E (8)
Flip-Flops Machine Reg. Reg.
Cycle H (8) L (8)
Encoding Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
Power +5 V (ALU) (8) Program Counter (16)
Supply GND
Increment/Decrement
Address Latch (16)
X1 CLK
Timing and Control Reset
X2 GEN Address Buffer Data/Address Buffer
Control Status DMA
(8) (8)
CLK RD WR S0 S1 IO/M HLDA RESET OUT

OUT ALE A15 - A8 AD7 – AD0
HOLD RESET IN
READY Address Address/Data51
INTA RST6.5 TRAP
SID SOD
UsedUsed toINTR
hold
8-bitdata
data(i.e. temporary
RST7.5
• to store RST5.5 to perform arithmetic& logical operations.
data)
• Result during ALUis operation.
Interrupt
of operation in Accumulator.Serial I/O Control
Control
stored
Instructio When Instruction is fetched from

n Reg. (8)
memory, itWis(8)loadedZin(8)the
Instruction Registor
Temp. (IR).
Reg. Temp. Reg.
Instruction S Z AC
B (8) P
C (8) CY
Decoder Reg. Reg.
Flag (5) and
Register Select
D (8)
Instruction decoderEdecodes
(8)
Cycle the information
H (8) present
L (8) in the
Encoding InstructionReg.
register. Reg.
Logic Unit
(ALU) (8) Program Counter (16)
Increment/Decrement
Address Latch (16)
X1 CLK
GEN Address Buffer Data/Address Buffer
• Control
Performs Status
Computing DMA
Functions.
(8) (8)
• Accumulator, Temporary Register
CLK RD WR S0 S1 HLDA RESET OUT
OUT
and Flag Registers
ALE
are part of ALU. A15 - A8 AD7 – AD0
HOLD RESET IN
INTA RST6.5 TRAP
A multiplexer pulls out the right group
of bits, depending on the instruction.
Instructio
n Reg. (8)
W (8) Z (8)
• • Two additional 8-bit register,
Each register can hold 8-bit data. which holds Temp. Reg. Temp. Reg.
• the
Thesetemporary
registers candataworkduring execution
Instruction of
in pair to hold 16- B (8) C (8)
Decoder Reg. Reg.
some instructions.
bit data and Flagtheir (5)
pairing combination
and is
Register Select
D (8) E (8)
• They are used
like B-C, D-E & H-L. internally,
Flip-Flops so they are
Machine not Reg. Reg.
available to the programmer. Cycle H (8) L (8)
It increments the program counter as Encoding Reg. Reg.
instructions
16-bit
It register
is a 16-bit execute,
Arithmetic
used
register increments
to store
works the which
like stack, andis
memory Stack Pointer (16)
decrements
address
always the stack
location Logic pointer
of Unit
the
incremented/decremented as needed,
next instruction andbe
to
by 2 during
supports
executed.
push the 16-bit
& pop operations. increment and decrement
Increment/Decrement
instructions. Address Latch (16)
• The content stored in the SP and PC is
X1 CLK
loaded
Timing and into the Address BufferResetand
Control
Control Buffer.
Data/Address Status DMA
(8) (8)
• The memory and I/O chips are connected
CLK RD WR S 0 S1 HLDA RESET OUT
to
OUT
these buses
ALE
that can exchange the A15 - A8 AD7 – AD0
HOLD RESET IN
READY
data. Address Address/Data53
INTA RST6.5 TRAP
A multiplexer pulls out the right group
of bits, depending on the instruction.
Instructio
n Reg. (8)
W (8) Z (8)
• • Two additional 8-bit register,
Each register can hold 8-bit data. which holds Temp. Reg. Temp. Reg.
• the
Thesetemporary
registers candataworkduring execution
Instruction of
in pair to hold 16- B (8) C (8)
Decoder Reg. Reg.
some instructions.
bit data and Flagtheir (5)
pairing combination
and is
Register Select
D (8) E (8)
• They are used
like B-C, D-E & H-L. internally,
Flip-Flops so they are
Machine not Reg. Reg.
available to the programmer. Cycle H (8) L (8)
It increments the program counter as Encoding Reg. Reg.
instructions
16-bit
It register
is a 16-bit execute,
Arithmetic
used
register increments
to store
works the which
like stack, andis
memory Stack Pointer (16)
decrements
address
always the stack
location Logic pointer
of Unit
the
incremented/decremented as needed,
next instruction andbe
to
by 2 during
supports
executed.
push the 16-bit
& pop operations. increment and decrement
Increment/Decrement
instructions. Address Latch (16)
• The content stored in the SP and PC is
X1 CLK
loaded
Timing and into the Address BufferResetand
Control
Control Buffer.
Data/Address Status DMA
(8) (8)
• The memory and I/O chips are connected
CLK RD WR S 0 S1 HLDA RESET OUT
to
OUT
these buses
ALE
that can exchange the A15 - A8 AD7 – AD0
HOLD RESET IN
READY
data. Address Address/Data54
INTA RST6.5 TRAP
Instructio
n Reg. (8)
W (8) Z (8)
Decoder Reg. Reg.
Flag (5) and
Register Select
D (8) E (8)
Cycle H (8) L (8)
Encoding Reg. Reg.
This unit synchronizes all the microprocessor operations
Arithmetic
with the
Stack Pointer (16)
clock and generates control signal necessary for communication
Logic Unit
betweenInput signal (ALU) (8) & peripheral.
to synchronize
microprocessor microprocessor Program Counter (16)
Perform synchronization
Frequency Control
Read/write Signals
either to/from memory orsignal
peripherals. Increment/Decrement
with with peripheral
peripheral
Shows device.
device. DMA control
read/write status to/from
Address Latch Enable control signal memory or I/O.
Address Latch (16)
X1 CLK
Signal to RESET microprocessor
Timing and Control Reset and other devicesData/Address
connected to
X2 GEN Address Buffer Buffer
Control Status DMA
it. (8) (8)

HOLD RESET IN
INTA RST6.5 TRAP
Instructio
n Reg. (8)
W (8) Z (8)
Decoder Reg. Reg.
Flag (5) and
Register Select
D (8) E (8)
Cycle H (8) L (8)
Encoding Reg. Reg.
Logic Unit
Increment/Decrement
Address Latch (16)
X1 CLK
Control Status DMA
(8) (8)

HOLD RESET IN
INTA RST6.5 TRAP
•
Accumulator It
(8)controls
Temp.the
Reg.interrupts
(8) duringInstructio
a process. Multiplexer
It controls
n Reg. the
(8) serial data
• There are 5 interrupt signals in 8085 microprocessor:W (8) communication by
Z (8)
using two
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR. instructions: Temp. Reg. Temp. Reg.
i. SID (Serial input data) B (8)
Instruction C (8)
Decoder
ii. SOD (Serial output data) Reg. Reg.
Flag (5) and
Register Select
D (8) E (8)
Cycle H (8) L (8)
Encoding Reg. Reg.
Logic Unit
Increment/Decrement
Address Latch (16)
X1 CLK
Control Status DMA
(8) (8)

HOLD RESET IN
INTA RST6.5 TRAP
Instructio
n Reg. (8)
W (8) Z (8)
Decoder Reg. Reg.
Register Select
Flag (5) and D (8) E (8)
Cycle H (8) L (8)
Encoding Reg. Reg.
Logic Unit
Power +5 V (ALU) (8) Program Counter (16)
Supply GND
Increment/Decrement
Address Latch (16)
X1 CLK
Control Status DMA
(8) (8)
CLK RD WR S0 S1 IO/M HLDA RESET OUT

HOLD RESET IN
T-States
Machine Cycle
Instruction Cycle
59
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T-States, Machine and Instruction Cycle
T-States Operation performed in one clock period.
Time required by the microprocessor to complete

Machine Cycle an operation.
Time required to complete execution of an

Instruction Cycle instruction.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
T-States
 “T-States are defined as operation performed in one clock period.”
 These sub-divisions are internal states synchronized with system
clock & each T-state is precisely equal to one clock period.
T-State-1 T-State-2 T-State-3 T-State-4
CLK
Clock Period
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
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of Engineering
Engineering &
& Technology
Technology
Machine Cycle
 “Machine Cycle is defined as time required by the microprocessor
to complete an operation.“ h m/m Read
IO
w rite
Fetc
 This cycle may consist 3 to 6 T-states.
 The basic microprocessor operation such as reading a byte from

I/O port or writing a byte to memory.
Opcode Fetch Memory Read I/O Write

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK
Machine Cycle-1 Machine Cycle-2 Machine Cycle-3
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Instruction Cycle
 “Instruction Cycle is defined as time required to complete
execution of an instruction. “
 In 8085 microprocessor instruction cycle consists of 1 to 6
Machine Cycles or 1 to 6 operations.
Instruction Cycle
T1 T2 T3 T4
CLK
Fetch Cycle Execute Cycle
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Demultiplexing AD0-AD7
64
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Demultiplexing AD0-AD7
A15 0 A15
0 A14
1 A13
0 High-Order
A12
8085 Microprocessor
0 A11 Address Bus

0 A10
0 A9
A8 0 A8
Enable G ALE=1
ALE
AD7 0 A7
0 A6 Address Bus
0 A5
0 A4 Low-Order
1 A3
0 A2 Address Bus
1 A1
AD0 1 A0
0 ALE= 0
1 D7 Data Bus
0 D6
0 D5
1 D4 Data Bus
1 D3
1 D2
1 D1 65
D0
Memory Interfacing
66
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing
 When we are executing any instruction, we need microprocessor
to access the memory for reading instruction codes and the data
stored in the memory.
 For this, both the memory and the microprocessor requires some
signals to read/write to or from registers.
 The interfacing circuit therefore, should be designed in such a way
that it matches the memory signal requirements with the signals
of the microprocessor.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Timing Diagram
68
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Opcode Fetch
T1 T2 T3 T4
CLK
Timing Diagram: Opcode Fetch
A15
High order memory address Unspecified
A8
AD7 Low order
Opcode
AD0 M/m addr.
ALE
IO/M
RD
69
Memory read cycle
T1 T2 T3 T4
Timing Diagram: Memory Read Cycle
CLK
A15
High order memory address
A8
AD7 Low order
Data from memory
AD0 M/m addr. S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
ALE
IO/M
S0 IO/M=0, S1=1 , S0=0
S1
RD
70
Memory write cycle
T1 T2 T3 T4
Timing Diagram: Memory Write Cycle
CLK
A15
High order memory address
A8
AD7 Low order Data from
AD0 M/m addr. Microprocessor S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
ALE
IO/M
S1 IO/M=0, S1=0 , S0=1
S0
WR
71
Memory Interfacing
72
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory structure
Block diagram of Memory Device: RAM
N=Number of Register
Data Inputs M=Word Length
E.g.
WR If a memory is having
Input Buffer
CS address lines=13
A10
Internal Decoder
data lines=8
then
Address NXM 1. number of registers / memory
Input Memory locations = N=213 = 8192
2. word length M= 8 bit
A0 Therefore, N X M= 8192 X 8
Output Buffer
RD
Data Output
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory structure
No. of Lines Memory size(bytes) No. of Lines Memory size(bytes)
1 2 9 512
2 4 10 1024=1k
3 8 11 2048=2k
4 16 12 4096=4k
5 32 13 8192=8k
6 64 14 16384=16k
7 128 15 32768=32k
8 256 16 65536=64k
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing
 8085 can access 64K of memory, thus address bus is of 16-bit.
 It is not always necessary to use full 64K address space. The total
memory size depends upon the application.
 Generally EPROM is used as a program memory and RAM is used
as data memory.
 When both are used then total 64K address will be shared by
both.
 The capacity of program memory and data memory depends on
the application.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing
 It is not always necessary to select 1 EPROM and 1 RAM. We can
have multiple EPROMs and multiple RAMs as per the requirement
of application.
 We can place EPROM / RAM anywhere in full 64 Kbytes address
space.
 Program memory (EPROM) should be located from address
0000H, since reset address of 8085 microprocessor is 0000H.
 It is not always necessary to locate EPROM and RAM in
consecutive memory addresses.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing: Example 1
Interface 4kB of EPROM with starting address from 0000H and 2kB of
RAM with starting address followed by EPROM
Step-1: To calculate no. of EPROM and RAM chip required
Total EPROM required = 4kB
Chip size available = 4kB
No. of chips required = 4kB/4kB=1
Total RAM required = 2kB

Chip Size Available = 2kB
No. of Chips required = 2kB/2kB=1
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Step-2: To calculate starting and ending address of EPROM
EPROM Chip-1:
Starting Address = 0000H
Chip Size = 4kB (i.e. address Line=12, m/m = 2 12 = 4096B = 4k)
Ending Address = 0FFFH
Step-3: To calculate starting and ending address of RAM
RAM Chip-1:
Starting address = Ending address of EPROM +1
= 0FFFH+1
= 1000H
Chip Size = 2kB = 07FFH
Ending address = 1000H+07FFH
= 17FFH
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
4k End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1000 H
RAM
2k End
Address
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
17FF H
EPROM chip size = 4kB & RAM chip size = 2kB

smaller chip size RAM = 2kB = 211
Thus neglect lower 11 address lines (A0 to A10), and consider A11 to A15 for Decoding.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
A A A A A A A A A A A A A A A A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
EPROM
• Required Address Lines: A11 to A15.
• Now, EPROM has two Possibilities, either 00000 b or 00001 b.
• Therefore, it requires Y0 and Y1 outputs of decoder.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
A A A A A A A A A A A A A A A A

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
1000 H
RAM End
Address
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
17FF H
RAM has 00010 b, hence it requires Y2 output of decoder.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing: Example 1 Implementation
Step-5:
RD
IO/M
OE A0 - A10
WR
RD
EPROM
D0
-
Y0 00000 D7
To EPROM
A15 Y1
00001
A14
Y2 To RAM D0 – D7 A0 - A10
A13 5:32 00010
Decoder
A12 OE RAM
A11
82
Interface 16kB of EPROM with chip size of 8kB and starting address
from 0000H and 8kB of RAM with starting address followed by
EPROM.
Step-1: To calculate no. of EPROM and RAM chip required
Total EPROM required =16kB
No. of chips required = 16kB/8kB = 2
Total RAM required = 8kB

No. of chips required = 8kB/8kB = 1
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Step-2: To calculate starting and ending address of EPROM
EPROM Chip-1:
Starting Address = 0000H
Chip Size = 8kB (i.e. address Line=13, m/m=213 =8192B =8k)
Ending Address = 1FFFH
EPROM Chip-2:
Starting Address =1FFFH + 1 = 2000H
Chip Size = 1FFFH
Ending Address = 2000+1FFFH = 3FFFH
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Step-3:RAM Chip-1:
Starting Address = EPROM ending address + 1
Starting Address = 3FFFH+1 = 4000H
Chip Size = 8kB (i.e. address Line =13, m/m=213 = 8192B =8k)
Chip Size = 1FFFH
Ending Address = 4000h+1FFFH = 5FFFH
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
1 End
Address
1FFF H 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM
2 End
Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM End
Address 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
5FFF H
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Step-5:Interface Implementation
 EPROM chip size = RAM chip size = 8kB = 213
 Therefore, neglect lower 13 address lines (i.e. A0 to A12) and
consider only A13 to A15 for decoding.
EPROM CHIP-01 000
EPROM CHIP-02 001
RAM CHIP-01 010 Y0 To EPROM Chip-1
Y1 To EPROM Chip-2
A15 Y2 To RAM Chip-1

3:8
A14 Decoder
A13
Y7
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
1 End
Address
1FFF H 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM
2 End
Address
3FFF H 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM End
Address
5FFF H 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Memory Interfacing: Example 2 Implementation
Step-5:
RD A0 - A12
OE
IO/M
EPROM
CHIP-1
WR D0
RD -
D7
D0 – D7 A0 - A12
Y0 000 To EPROM CHIP-1 OE

EPROM
Y1 001 To EPROM CHIP-2 CHIP-2
A15
Y2 010 To RAM
A14 3:8
Decoder
A13
D0 – D7 A0 - A12
OE RAM
Exercise: Memory Interface Example
1. Draw the interfacing of a 4KB EPROM having a starting address
2000h and two 2KB static RAMs having starting addresses 4000h
and 8000h, respectively, with 8085 microprocessor.
2. Design an 8085 microprocessor system such that it should
contain 16KB of EPROM and 4KB of RAM with starting addresses
0000H and 4000H respectively. Use two 8KB of EPROMs (2764)
and two 2KB of RAMs (6116) for this system.
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Exercise: Example 1
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 2000 H
1 End
Address
2FFF H 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM 1 End
Address 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
47FF H
Start
Address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8000 H
RAM 2 End
Address 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
87FF H
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
Exercise: Example 1
Step-5:
RD A0 - A12
OE
IO/M
EPROM
CHIP
WR D0
RD -
D7
D0 – D7 A0 - A12
Y0 00100 OE
To EPROM
Y1 RAM-1
00101
A15
Y2 To RAM-1
A14 5:32 01000
A13 Decoder
Y3 To RAM-2
A12 10000
D0 – D7 A0 - A12
A11
OE RAM-2
Exercise: Example 2
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
1 End
Address
1FFF H 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM
2 End
Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM 1 End
Address 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
47FF H
Start
Address
4800 H 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
RAM 2 End
Address
4FFF H 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Exercise: Example 2
Step-5: A0 - A10
RD OE
IO/M D0 EPROM-1
-
D7
WR
RD A0 - A10
OE
D0 EPROM-2
-
D7
Y0 00011
EPROM-1
Y 00100
1
D0 – D7 A0 - A10
A15 OE
RAM-1
A14 5:32 EPROM-2
Y2 00101
A13 Decoder
A12 Y3 01000 To RAM-1
A11
D0 – D7 A0 - A10
Y4 10000 To RAM-2
OE RAM-2
Generating Control Signals
0 0 0 Invalid
0 0 1 MEMR
IO/M 0
MEMR
RD 0
8085
WR 1
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 0 Invalid
0 0 1 MEMR
0 1 0 MEMW
IO/M 0
MEMR
RD 1
8085
WR 0 MEMW
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 0 Invalid
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
IO/M 0
MEMR
RD 1
8085
WR 1 MEMW
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 0 Invalid
IO/M 1
MEMR
RD 0
8085
WR 0 MEMW
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
IO/M 1
MEMR
RD 0
8085
WR 1 MEMW
IOR
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
1 1 0 IOW
IO/M 1
MEMR
RD 1
8085
WR 0 MEMW
IOR
IOW
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
IO/M 1
MEMR
RD 1
8085
WR 1 MEMW
IOR
IOW
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology
0 0 0 HLT
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 0 HLT
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
Unit-3
Unit-3 8085
8085 Microprocessor
Darshan Institute
Institute of
of Engineering
Engineering &
& Technology
Technology

Unit-3 8085 Microprocessor

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Microprocessor and Interfacing

Prof. Swati R. Sharma

General Purpose Registers

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

 6 general purpose registers to store 8-bit data B, C, D, E, H & L.

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

 5 Flag Register for set/reset operations.

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

8085 MPU Output Real

8085 MPU Output Real

8085 MPU Output Real

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

CLK RD WR S0 S1 IO/M HLDA RESET OUT

Instructio When Instruction is fetched from

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

CLK RD WR S0 S1 HLDA RESET OUT

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

CLK RD WR S0 S1 HLDA RESET OUT

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

CLK RD WR S0 S1 HLDA RESET OUT

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus

CLK RD WR S0 S1 IO/M HLDA RESET OUT

Time required by the microprocessor to complete

Time required to complete execution of an

T-State-1 T-State-2 T-State-3 T-State-4

 This cycle may consist 3 to 6 T-states.

 The basic microprocessor operation such as reading a byte from

Opcode Fetch Memory Read I/O Write

Machine Cycle-1 Machine Cycle-2 Machine Cycle-3

Fetch Cycle Execute Cycle

0 A11 Address Bus

Total RAM required = 2kB

EPROM chip size = 4kB & RAM chip size = 2kB

RAM has 00010 b, hence it requires Y2 output of decoder.

Total RAM required = 8kB

A15 Y2 To RAM Chip-1

Y0 000 To EPROM CHIP-1 OE

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