COMBINATIONAL &

SEQUENTIAL CIRCUITS
COMBINATIONAL CIRCUITS
 Digital Components

• The main thing to remember is that

combinations of gates implement Boolean
functions.
• The circuit below implements the Boolean
function:

We simplify our Boolean expressions so

that we can create simpler circuits.

4
 Combinational Circuits
• We have designed a circuit that implements the
Boolean function:

• This circuit is an example of a combinational logic

circuit.
• Combinational logic circuits produce a specified
output (almost) at the instant when input values are
applied.
– In a later section, we will explore circuits where this is not
the case.

5
 Combinational Circuits

• Combinational logic circuits give us

many useful devices.
• One of the simplest is the HALF
ADDER, which finds the sum of two
bits.
• We can gain some insight as to the
construction of a half adder by
looking at its truth table, shown at
the right.

6
 Combinational Circuits

• As we see, the sum can be

found using the XOR
operation and the carry
using the AND operation.

7
 Combinational Circuits

• We can change our half

adder into to a full adder
by including gates for
processing the carry bit.
• The truth table for a full
adder is shown at the
right.

8
 Combinational Circuits

• How can we change the

HALF ADDER shown
below to make it a FULL
ADDER?

9
 Combinational Circuits

• Here’s our completed full adder.

10
SEQUENTIAL CIRCUITS
 LOGIC CIRCUITS

 Combinational Logic
o The main characteristic of combinational logic circuits is that their output values depend
on their present input values ONLY like in adders.

 Sequential Logic
o Sequential logic circuits differ from combinational logic circuits because they contain
memory elements so that their output values depend on both present and past input
values.
 TIME
• Until now: In Combinational circuits, we have essentially ignored the issue
of time.
• We have assumed that our digital logic circuits perform their computations
instantaneously.
• Our digital logic circuits have been “stateless” – Once you present a new
input, they forget everything about previous inputs.
• In reality, time is an important issue.
• Even our logic gates induce a small amount of delay (on the order of a few
nanoseconds).
• For much of what we do – we actually want our circuits to have some form
of memory.
 ASYNCHRONOUS VS SYNCHRONOUS

 Sequential circuits can be Asynchronous or synchronous.

Asynchronous sequential circuits change their states and output

values whenever a change in input values occurs.

Synchronous sequential circuits change their states and output

values at fixed points of time, i.e. clock signals.
 MEMORY DEVICES

 Latches
 A latch is a memory element whose excitation signals (input control
signals) control the state of the device.
 A latch has 2 stages set and reset.
o Set stage sets the output to 1.

o Reset stage set the output to 0.

 Flip-flops
 A flip-flop is a memory device that has clock signals control the state
of the device.
 MEMORY DEVICES

 In the same way that ;

 GATES are the building blocks of combinatorial circuits e.g Adders,

 LATCHES & FLIP-FLOPS are the building blocks of sequential circuits.

 While GATES has to be built directly from transistors;

 Latches can be built from Gates, and

 Flip-flops can be built from Latches.

 This fact will make it somewhat easier to understand latches and flip-flops.

 Both latches and flip-flops are circuit elements whose OUTPUT depends not
only on the current inputs, but also on previous inputs and outputs.

 The difference between a latch and a flip-flop is that a latch does not have
a clock signal, whereas a flip-flop always does.
 SEQUENTIAL CIRCUITS

• Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

• Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock
 LATCH

 How can we make a circuit out of gates that is not combinational?

 The answer is feed-back.

 Memory relies on a concept called feedback.

 Which means that we create loops in the circuit diagrams so that output

values depend, indirectly, on themselves.

 This latch is called SR-latch, which stands for set and reset.

 SR - Latch
S R Q0 Q Q’
0
Initial Value
0 0 0 0 1 Q = Q0
R 0
Q

1
0 Q
S

Initial Value
 SR - Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0
Initial Value

R 0 1
Q

S Q
0 0
 SR - Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
Initial Value 0 1 0 0 1 Q=0
R 1 0
Q

S Q
0 1
 SR - Latch
S R Q0 Q Q’
S=R=0
0 0 0 0 1
Q = Q0
0 0 1 1 0
Initial Value 0 1 0 0 1 Q=0
R 1
R=1
1 0 1 1 0 1 Q=0
Q

S Q
0 0
 SR - Latch
S R Q0 Q Q’
S=R=0
0 0 0 0 1
Q = Q0
0 0 1 1 0
Initial Value 0 1 0 0 1
R 0
Q=0 R=1
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1

S Q
1 1
 SR - Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
Initial Value 0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0
 SR - Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
Initial Value 0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10
 SR - Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
Initial Value 0 1 0 0 1
R 1
Q=0
10 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0
 SR - Latch
S R Q
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q=Q’=0 Invalid

Once set, the output will remain at 1 (remembers its state) even though the S input goes
low.
Similarly, Once reset, the output will remain at 0 (remembers its state) even though the R
input goes low.
Invalid input shows that we could have ideally 1 input high & 1 input low in order to set &
reset. Also Q & its complement cannot be same for same value of inputs. So it is an invalid
condition.
 SR Flip Flop

• SR Latch with Control Input

Clock controlled flip-flop changes its state only when the clock C is high.

C S R Q
R R
Q 0 x x Q0 No change
C 1 0 0 Q0 No change
S Q 1 0 1 0 Reset
S
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
 D Flip Flop
• The D flip-flop is the modification of the SR flip flop which is shown in the figure.
• The input D goes directly into the input S and the complement of the input D goes
to the input R.
• The D input is sampled during the existence of a clock pulse.
– If it is 1, then the flip-flop is switched to the set state.

– If it is 0, then the flip-flop switches to the clear or reset state.

D S
Q
C
R Q
 D Flip Flop
• D Flip Flop (D = Data) Timing Diagram
Q follows D, when clock is high
C
D S
Q D
C
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set
 Flip Flop Vs Latch

 A Flip Flop is a clocked latch i.e. Flip Flop = latch + clock

 Latches are building blocks of sequential circuits & these can be made by Logic Gates
Whereas Flip Flops are also building blocks of sequential circuits but these can be built
from Latches.
 Latch continuously checks for inputs & changes the output whenever there is a change
in input. Flip Flop also continuously checks input, but changes the output time
determined by clock. [so, even though if inputs are changed, it may not change the
output at the same time].
 When there are multiple inputs/outputs, flip flop is used, that controls the sequence of
the circuit with the help of a clock.
 That is Flip Flop mechanism is used to synchronize circuits so that the data does not
change unnecessarily.
ALLAH HAFIZ