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AMBA Protocols Introduction

The document discusses different bus protocols, including APB, AHB, and AXI. APB is the simplest protocol, connecting one master to multiple slaves with simple read and write transactions. AHB is faster than APB and supports multiple masters and slaves through a shared bus. AXI is the most advanced protocol, separating traffic into different channels to allow different components to interact without shared busses.

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yoav
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61 views

AMBA Protocols Introduction

The document discusses different bus protocols, including APB, AHB, and AXI. APB is the simplest protocol, connecting one master to multiple slaves with simple read and write transactions. AHB is faster than APB and supports multiple masters and slaves through a shared bus. AXI is the most advanced protocol, separating traffic into different channels to allow different components to interact without shared busses.

Uploaded by

yoav
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 14

ARM

AMBA
protocols
Yoav Lurie
10.05.20
Contents
AMBA FAMILY
APB
AHB
AXI

2
AMBA family
AMBA – Advanced Microcontroller Bus Architecture

3
APB protocol
Advanced Peripheral Bus
Connects one master to (several) slaves – in our implementation only 1 slave
Each transaction contains its address and data
Simple, fairly slow and not very advanced

4
APB protocol signals
PADDR[x:0]
PPROT[2:0]
PSELx
PENABLE
PWRITE
PWDATA[31:0]
PSTRB[3:0]
PREADY
PRDATA[31:0]
PSLVERR

5
APB transaction flow

Write operation
Read operation

6
AHB – Advanced High-performance Bus
Originally, connected several masters to several slaves through shared bus

Our implementation – one master to one slave – AHB lite

Faster than APB, simple to implement. Still used in many IPs

7
AHB protocol signals
HADDR[x:0]
HBURST[2:0]
HMASTLOCK
HPROT[3:0] HPROT[6:4]
HSIZE[2:0]
HNONSEC
HEXCL
HMASTER[3:0]
HTRANS[1:0]
HWDATA[31:0]
HWRITE

8
AHB write transaction flow

9
AHB read transaction flow

10
AXI – Advanced eXtensible Interface
Each component interacts with a central interconnect – no shared busses.
Traffic is separated into 5 channels
AW – Address Write
W – Write Data
B – Response Data
AR – Address Read
R – Read Data (with integrated response)
Channel items are associated by id field

11
AXI protocol signals
Address Phase signals A(W/R)PROT [3:0]

A(W/R)ID [x:0] A(W/R)QOS [4:0]

A(W/R)ADDR [x:0] A(W/R)VALID

A(W/R)LEN [7:0] A(W/R)READY

A(W/R)SIZE [2:0] Optional signals

A(W/R)BURST [1:0] A(W/R)REGION [3:0]

A(W/R)LOCK [1:0] A(W/R)USER [x:0]

A(W/R)CACHE [3:0]

12
AXI protocol signals
Data channels RRESP

(W/R)ID [x:0] Write Response

(W/R)DATA [x:0] BID [x:0]

(W/R)LAST BRESP [1:0]

(W/R)USER [x:0] BUSER [x:0]

(W/R)VALID BVALID

(W/R) READY BREADY

Only Write
WSTRB [data/8:0]

Only Read

13
AXI waves

14

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