Serial Communication

Protocols part 2

Nasif M.

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 Serial Communication Protocols
• A variety of communication protocols have been developed based on serial
communication in the past few decades. Some of them are:
• SPI – Serial Peripheral Interface: It is a three-wire based communication
system. One wire each for Master to slave and Vice-versa, and one for clock
pulses. There is an additional SS (Slave Select) line, which is mostly used
when we want to send/receive data between multiple ICs.
• I2C – Inter-Integrated Circuit: Pronounced eye-two-see or eye-square-see,
this is an advanced form of USART. The transmission speeds can be as high as
a whopping 400KHz. The I2C bus has two wires – one for clock, and the other
is the data line, which is bi-directional. It is invented by Philips.

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Serial Communication Protocols
• Ethernet: Used mostly in LAN connections, the bus consists of 8 lines, or 4
Tx/Rx pairs.
• Universal serial bus (USB): This is the most popular of all. Is used for
virtually all type of connections. The bus has 4 lines: VCC, Ground, Data+,
and Data-.
• RS-232 – Recommended Standard 232: The RS-232 is typically connected
using a DB9 connector, which has 9 pins, out of which 5 are input, 3 are
output, and one is Ground. You can still find this so-called “Serial” port in
some old PCs. In our upcoming posts, we will discuss mainly about RS232
and USART of AVR microcontrollers.

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 Serial Peripheral Interface (SPI)
• Serial Peripheral Interface (SPI) is a synchronous serial data protocol used by
microcontrollers for communicating with one or more peripheral devices quickly
over short distances. It can also be used for communication between two
microcontrollers.
• With an SPI connection there is always one master device (usually a
microcontroller) which controls the peripheral devices. Typically there are three
lines common to all the devices:
MISO (Master In Slave Out) - The Slave line for sending data to the master,
MOSI (Master Out Slave In) - The Master line for sending data to the
peripherals,
SCK (Serial Clock) - The clock pulses which synchronize data transmission
generated by the master and one line specific for every device:
SS (Slave Select/ Chip select) - the pin on each device that the master can use to
enable and disable specific devices. 4
Serial Peripheral Interface (SPI)

Figure: SPI communication protocol

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Serial Peripheral Interface (SPI)

Figure : Multiple slaves are connected with master using SPI protocol
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Advantages of SPI
• The receiver/sender hardware can be a simple shift register
• It supports multiple slaves

Disadvantages of SPI
• The master must control all communications (slaves can’t talk directly to
each other)
• It usually requires separate SS lines to each slave, which can be
problematic if numerous slaves are needed

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 I2C Protocol
• The Inter-integrated Circuit (I2C) Protocol is a protocol intended to allow
multiple “slave” digital integrated circuits (“chips”) to communicate with one
or more “master” chips. Like the Serial Peripheral Interface (SPI), it is only
intended for short distance communications within a single device. Like
Asynchronous Serial Interfaces (such as RS-232 or UARTs), it only requires
two signal wires to exchange information.
• I2C requires a mere two wires, like asynchronous serial, but those two wires
can support up to 1008 slave devices. Also, unlike SPI, I2C can support a
multi-master system, allowing more than one master to communicate with
all devices on the bus (although the master devices can’t talk to each other
over the bus and must take turns using the bus lines).
• I2C specifies 2 address lengths, 7 and 10 bits, which gives a theoretical
maximum of 128 and 1024 distinct address, respectively. However, there are
a few reserved addresses, such as 0x00 (general call). This further limits the
address space. 9
 I2C Protocol
• The I2C protocol involves using two lines to send and receive data: a
serial clock pin (SCL) and a serial data pin (SDA) over which data is sent
between the two devices. 

Figure: I2C Protocol

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Advantages of I2C
1. Flexibility – The I2C protocol supports multi-master, multi-slave
communication. More than one master IC controlling and communicating
with the slave ICs can speed things up and add more functionalities to the
embedded system.
2. Addressing feature –Another advantage of the I2C protocol lies in its
inherent ability to use chip addressing. It means that it is possible to add
components to the bus without any complexity. It eliminates the necessity of
CS (chip select) lines.
3. Simplicity – I2C protocol doesn’t complicate the design. It requires only
two bidirectional signal lines to establish communication among multiple
devices.
4. Reliable Data Transfer - ACK/NACK bit gives confirmation that each frame is
transferred successfully
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How I2C works
With I2C, data is transferred in messages. Messages are broken up into
frames of data. Each message has an address frame that contains the binary
address of the slave, and one or more data frames that contain the data
being transmitted. The message also includes start and stop conditions,
read/write bits, and ACK/NACK bits between each data frame:

Figure: Instruction sequence data from master to slave 12

Handshaking Process in I2C Protocol
• In I2C for each byte, an acknowledgment needs to be sent by the receiver,
this acknowledgment bit is a proof that data is properly received by the
receiver and it wants to continue the communication.
• A master starts the communication to assert a start condition on the bus.
After the start condition master is transmitted a 10-bit address with
associated a read or write bits.
• After the transmission of the address byte, master release the data lines,
which allows the receiver (slave) to give the acknowledgment.
• Each slave compares the address sent from the master to its own address. If
the address matches, the slave returns an ACK bit.
• After receiving the Acknowledgment bit, Master continue the read or write
operation.
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Handshaking Process in I2C Protocol - Acknowledge (ACK) and Not Acknowledge (NACK)

Some scenario, where NACK bit is generated-

• When the receiver is unable to receive, in that situation it generates a NACK
bit to stop the communication.
• During the communication, if the receiver gets any data or commands which
are not understood by the receiver then it generates a NACK bit.
• When Master is a receiver and reads the data from the slave, then after the
reading of whole data it asserts a NACK bit on data lines to stop the
communication.
• If there is no device present in the I2C bus of the same address which is
transmitted by the master, then the master will not get the acknowledge by
any slave and treat this situation as NACK.

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I2C WRITE operation
• In I2C before the performing, the WRITE operation master has to assert a start
condition on I2C bus with the slave’s address and write control bit (for write
operation control bit will be 0).
• If the transmitted address match with any slave which connected to the I2C bus
then master receives an acknowledge (ACK) bit. After getting the ACK bit
master send the address of the register, where it wishes to write, the slave will
acknowledge again, letting the master know it is ready for the WRITE operation.
• After getting this acknowledgment, the master will start sending the data to the
slave. Master will get the acknowledgment of each transmitted byte of data.
• When the master has sent all the data then the master end the transmission
with a STOP condition.

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I2C WRITE operation

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Figure: Sequence diagram
showing Master to slave
WRITE operation
(send 2 data frame)

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I2C READ operation
• Here, master asserts the start condition before the READ operation. After
the start condition master transmit the slave address with READ control bit
(for read operation control bit will be 1), if the transmitted address match
with any device in the I2C bus then it acknowledges to the master.
• After getting ACK bit, master release the data bus but continue sending the
clock pulse, in that situation master become receiver and slave become the
transmitter.
• In the READ operation, the master gives the acknowledgment to the slave on
the receiving of every byte of data to let the slave know that it is ready for
more data. Once the master has received the number of bytes which it is
expecting, it will send a NACK bit to release the BUS and send the STOP
condition to halt the communication.

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I2C READ operation

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Figure: Sequence diagram
showing Master to slave READ
operation
(Receive 3 data frame)

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Exercise: Master (index:2H) send data (char ‘hat’) to the slave (index:8H).
Draw the corresponding sequence diagram.
Decimal ASCII Chart Decimal ASCII Chart

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Exercise: Master (index:3H) receive 5 byte data (char ‘water’) from the
slave (index:9H). Draw the corresponding sequence diagram.
Decimal ASCII Chart

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I2C disadvantage
• Slower data transfer rate than SPI
• The size of the data frame is limited to 8 bits

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I2C Q and A
• Can masters talk to each other in a I2C BUS?
No.
Only one master can be active at once - this means that a master can only talk
to slaves and slaves can appropriately reply. To have a multi-master scenario,
there has to be relinquishment of master status by one device and acceptance
of master status by another device.

• Can slave talk to each other in a I2C BUS?

No.

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I2C Q and A
• Can multiple master talk to the slaves simultaneously?
For normal data transfer on the I2C bus only one master can be active. If for
some reason two masters initiate I2C command at the same time, in such case
each device needs to be able to cooperate with the fact that another device is
currently talking and the bus is therefore busy. There two techniques available:
a) Arbitration logic. If two devices start to communicate at the same time the
one writing more zeros to the bus wins the arbitration and the other device
immediately discontinues any operation on the bus.
b) Bus busy detection. Each device must detect an ongoing bus
communication and must not interrupt it. This is achieved by recognizing
traffic and waiting for a stop condition to appear before starting to talk on the
bus.
The winning master will control both data bus and clock.
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Reference
• http://www.circuitbasics.com/basics-of-the-i2c-communication-proto
col/
• https://aticleworld.com/i2c-bus-protocol-and-interface/

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