Design of testable

sequential circuits
 The increased complexity of embedded systems and
the reduced access to internal nodes has made it not
only more difficult to diagnose and locate faulty
components, but also the functions of embedded
components may be difficult to measure.
 Creating testable designs is key.
 A fault is testable if there exists a well-specified
procedure (e.g., test pattern generation ) to expose it .

 Two basic properties determine the testability of a

node:
1) controllability – ability to apply test patterns to the
inputs of a sub-circuit via the primary inputs of the
circuit.
2) observability– ability to observe the response of the
sub-circuit via the primary outputs of the circuit.
Controllability the controllability /observability
of a ckt can be enhanced by incorporating
some control gates and Input lines and by
adding Some output lines.
 Design for testability (DFT) refers to those
design techniques that make the task of
subsequent testing easier.

 DFT techniques can largely be divided into

two categories: a) ad hoc techniques and
b)structured (systematic)
techniques.
A)Ad-hoc methods
i) Inserting MUX s


ii) Using Tristate inverters

iii)Access to subset of a
logic (shift register)
 B) Structured methods:
 Scan– a) scan path technique

b)Level Sensitive Scan Design (LSSD)

 Random Access scan
 Partial Scan
 Built-in self-test
 Boundary scan

i) Scan path technique: The testing of sequential

circuits is complicated because of difficulties in
setting and checking the states of memory
elements.

To overcome this we modify the design of general

sequential circuits by setting the internal state.
 Figure 5.14 and 5.15
 When c=0, circuit operates in normal mode.
 When c=1, circuit operates in which elements are

connected together to form a shift register.

 The SW is double throw switch which lead to

memory element.
 Another technique is known as Raceless D type
flip flop.
 RACE– a difference in time delays of signal

propagation along different paths may cause

malfunction of an asynchronous network.
 It is caused by difference in delay times of gates.
 The raceless D-FF is controlled in the following way:
a) For normal mode operation C2 = 1 to block SI and C1
= 0 →1 to load DI( data input).
b) For shift register test mode C1 = 1 to block DI and C2
= 0 →1 to load SI. (scan input).
L1 and L2 are latches.
Level Sensitive Scan Design (LSSD):
 It is a latch-based design.

 It is insensitive to component timing variations such as

rise time, fall time, and delay.

 A logic circuit is level sensitive (LS) if the steady state

response to any allowed input change is independent

of the delays within the circuit.

fig: POLARITY HOLD LATCH

 Priority hold latch cant change state if C=0.
 If C=0 , o/p follows D.
 Shift register latch (SRL) is formed by adding a clocked
input to the priority hold latch and second latch to act as
a intermediate storage during shifting.
 As long as A=B=0 , L1 act as priority hold latch and act
as shift register when A=1 and B=0 to shift SI through
L1.
 Advantages of LSSD
a) The correct operation of the logic network is
independent of A.C. characteristic such as
clock rise time and fall time.
b) Network is combinational in nature as far as
test generation and testing is concerned.
c) The elimination of all hazards and races
greatly simplifies test generation.
Random Access Scan (RAS) technique
 In other scan techniques the flip flops are

connected in series during testing to form shift

registers.
 In RAS, each flip flop in a logic network is

selected individually by the address for control

and observation of its state.
 The basic memory element in a RAS is an

addressable latch.
Partial scan

 In FULL scan, all Flip flops in a circuit are

connected into one or more shift registers.
 The states of circuit can be controlled and
observed via primary inputs and outputs
respectively.

 In PARTIAL scan, only a subset of the circuit flip

flops are included in scan chain in order to
reduce the overhead associated with full scan
design.
 Two separate clocks: system clock and scan clock.
 In normal mode, scan enable signal at logic 0.
 In scan mode, scan enable signal at logic 1.
 Disadvantage of two clock partial scan is that the routing of two
separate clocks with small skews is very difficult.
 So, we go for
Partial scan using only
system clock.
 Figure 5.31
 The test sequence is obtained by shifting data into
the scan flip flops.
 This data together with contents of non scan flip
flops constitute the starting state of test sequence.
 The other patterns in sequence are obtained by
single bit shifting of contents of scan flip flops,
which form required circuit states.

 THE NUMBER OF VALID STATES MAY LIMIT THE

FAULT COVERAGE OBTAINED IN THIS TECHNIQUE.

Testable sequential circuit design using non scan techniques
First method:
 scan based circuit cannot be tested at its normal speed, because

test data have to be shifted in and out via scan path.

 For normal mode, test mode=0.

 Test mode =1, D flip flop data comes to the non subset of flip

flop and comes to output.

 Second method: for enhancing Controllability
and observability.

Enhanced controllability:
 The controllability is improved by selecting the

subset of flip flops such that the number of

cycles in state diagram is minimized. These flip
flops are called Controllable flip flops.
a) Test =0 , normal mode .
b) test=1, test mode.
 Enhanced observability: by selecting a set of
internal nodes that are testable because
faults at such nodes cannot propagated to
the primary outputs.
 These signals at these nodes are compressed

by an EXOR tree, the output of which is

available on an additional output line.
CROSS CHECK
 Cross check approach incorporates test circuitry

into basic cells used to implement VLSI design.

Boundary scan
 This method is used to resolve the problem of

controlling and observing the input and output

pins of chips used in assembling a system /
subsystem on PCB.
 It provides single serial scan paths through the

input/outputs pins of individual chips on a

board.
 The boundary scan cells are controlled by TAP

(Test Access Port) which has four inputs:

a)TCK b) TMS c) TDI
d)TDO
 The outputs of all shift registers stages are
stored in a latch in order to prevent the
change of information while data is being
shifted in and out.
 Boundary scan register is configured in three
types of test:
a)External test: it is used to test
interconnections for stuck at and bridging
faults. next figure
b) Internal test: it allows individual chips on
PCB to be tested.
c)Sample test: allows monitoring of data
flowing into and out of a chip.
 Figure 5.30

 Two separate clocks: system clock and scan

clock.
 In normal mode, scan enable signal at logic 0.
 In scan mode, scan enable signal at logic 1.
 Disadvantage of two clock partial scan is that
the routing of two separate clocks with small
skews is very difficult.
 So, we go for Partial scan using system scan.
 Figure 5.31
 The test sequence is obtained by shifting data into
the scan flip flops.
 This data together with contents of non scan flip
flops constitute the starting state of test sequence.
 The other patterns in sequence are obtained by
single bit shifting of contents of scan flip flops,
which form required circuit states.

 THE NUMBER OF VALID STATES MAY LIMIT THE

FAULT COVERAGE OBTAINED IN THIS TECHNIQUE.
 scan based circuit cannot be tested at its normal
speed, because test data have to be shifted in and
out via scan path.
Testable sequential circuit design using non scan
techniques

Fig 5.32
First method:
 For normal mode, test mode=0.
 Test mode =1, D flip flop data comes to the non

subset of flip flop and comes to output.

 Second method: for enhancing Controllability
and observability.

Enhanced controllability:
 The controllability is improved by selecting the

subset of flip flops such that the number of

cycles in state diagram is minimized. These flip
flops are called Controllable flip flops.
a) Test =0 , normal mode .
b) test=1, test mode.
 Enhanced observability: by selecting a set of
internal nodes that are testable because
faults at such nodes cannot propagated to
the primary outputs.
 These signals at these nodes are compressed

by an EXOR tree, the output of which is

available on an additional output line.