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Low-Power, High-Performance 64-Bit CMOS Priority Encoder Using Static-Dynamic Parallel Architecture

This document describes the design of a 64-bit priority encoder using a static-dynamic parallel look-ahead architecture. The conventional priority encoder architecture propagates priority tokens in a sequential manner, limiting performance. The new architecture introduces a 4-bit priority encoder cell and divides the 64-bit encoder into 8 groups with look-ahead signals to determine the highest priority input. Simulation results show the new architecture achieves up to 34% lower transistor count, 80% lower power consumption, and 53% higher performance compared to the conventional design.

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AbhishekKumar
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97 views

Low-Power, High-Performance 64-Bit CMOS Priority Encoder Using Static-Dynamic Parallel Architecture

This document describes the design of a 64-bit priority encoder using a static-dynamic parallel look-ahead architecture. The conventional priority encoder architecture propagates priority tokens in a sequential manner, limiting performance. The new architecture introduces a 4-bit priority encoder cell and divides the 64-bit encoder into 8 groups with look-ahead signals to determine the highest priority input. Simulation results show the new architecture achieves up to 34% lower transistor count, 80% lower power consumption, and 53% higher performance compared to the conventional design.

Uploaded by

AbhishekKumar
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Low-Power, High-Performance 64-bit CMOS Priority

Encoder Using Static-Dynamic Parallel Architecture

Abhishek Kumar Gupta(2019EEN2277)


About Priority Encoder
 The priority encoder (PE) is a fundamental circuit in digital systems, having
been used in many applications.

 Some of its applications include content addressable memories,


incrementers/decrementers, interconnection network routers and
comparators.

 Out of a number of requests a priority encoder selects only one of them to be


served.

 We have implemented a 64-bit encoder, which will have 64 inputs and


correspondingly 64 outputs. Only that output will be selected at a time,
whose priority is highest based on the request made.
Working of Priority Encoder
 In a multibit PE, the output of the ith bit is :
EPi = Di • Pi
where Di is the corresponding input data and Pi stands for the priority token.

 When the input of the lower significance bit is 0, the priority token is passed
into the next bit:
Pi = Di-1 • Pi-1
 The general expression of EPi can be written as:

 As an 8-bit PE with a three level look-ahead, the circuit implements the


following functions.
Working of Priority Encoder (contd.)

 Thus, at any instant, only one output will be high corresponding to the
priority of the input bits.
The Conventional Architecture

An 8-bit PE cell
The Conventional Architecture (contd.)
 In the basic 8-bit priority encoder cell, D0 has the highest priority and D7 has
the lowest priority.

 Pass Transistors logic and Domino logic circuitry are used to minimize number
of transistors and power dissipation respectively.

 This 8-bit priority encoder cell is used in a specific design manner in order to
design a 64-bit priority encoder.

 Or gates are used to generate look-ahead inputs to the 8-bit priority encoder
cell. These look ahead inputs will determine amongst which set of 8-inputs
the highest priority input is to be considered.
The Conventional Architecture (contd.)

 A 64-bit priority encoder with conventional


architecture
The Look Ahead Architecture
 The performance of conventional priority encoder circuits is usually limited
by the delay associated with the propagation of the priority token, however,
proper design in the architectural level can reduce the delay stages to the
order of O(log n).

 Furthermore, power dissipation and area pose an increasingly important


concern in modern circuit design, thus the development of suitable
techniques is essential.

 This new architecture introduces a new 64-bit priority encoder based in a


static dynamic parallel priority look-ahead architecture and a newly designed
4-bit PE cell.

 Compared to conventional architecture, it achieves up to 34% reduction in


transistors, 80% reduction in power and 53% improvement in performance.
The Look Ahead Architecture (contd.)

Fig1: 4-bit Feedback Priority Encoder(FBPE) Fig2: 8-bit Look-ahead Priority Encoder(L-PE) Fig3: 8-bit Data Priority Encoder(D-PE)
The Look Ahead Architecture (contd.)

 A 64-bit priority encoder with look-ahead


architecture
Simulation Results
 The power dissipation and time delay is calculated for the worst case, which
occurs at the input combination D0~D63 is 0x00 00 00 00 00 00 00 01.
 The transistors used while designing the circuit consists of nMOS transistors
with Ln = 60nm and Wn = 100nm, as well as pMOS transistors with Lp = 60nm
and Wp = 100nm.
 During simulation we have considered the clock frequency to be 1GHz.

64-bit PE Delay Power Dissipation Transistors Count

Conventional Design 671ps 103mW 790

Look-ahead Design 518 ps 23mW 580


Transient Response of the 64-bit PE
Scaling of parameters
   have designed the 64-bit PE in 65nm technology as compared to the 32nm
We
used by the author.
 Correspondingly, there is a deviation from the author’s simulation results and
the results obtained by us.
 Though, this deviation can be accounted for the scaling factor ‘S’ which is
due to the difference in the minimum channel length.
 Now, S = = = 2.03 and = 0.485 and = 0.245
 Correspondingly, the time delay ratio in 32nm technology should be times of
the time delay in 65nm technology and power should be times of the power
dissipation in 65nm technology.
 Now, Ratio of time delay = = 0.425 (which is nearly equal to 1/s).
 Now, Ratio of power dissipation = = 0.34 (which is nearly equal to 1/s2).
References
 1. C. H. Huang, J. S. Wang and Y. C. Huang, "Design of high-performance CMOS
priority encoders and incrementer/decrementers using multilevel lookahead and
multilevel folding techniques," in IEEE Journal of Solid-state Circuits, vol.37, no.1,
pp.63-76, Jan 2002.
 2. J.G. Delgado-Frias and J. Nyathi, "A high-performance encoder with priority
lookahead," in IEEE Transactions on Circuits and Systems I: Fundamental Theory and
Applications, vol.47, no.9, pp.1390-1393, Sep 2000.
 3. S. Abdel-Hafez and S. Harb, "A VLSI High-Performance Priority Encoder Using
Standard CMOS Library," in IEEE Transactions on Circuits and Systems II: Express Briefs,
vol.53, no.8, pp.597-601, Aug. 2006.
 4. J.S. Wang and C.H. Huang, “High-speed and low-power CMOS priority encoders,”
IEEE J. Solid-State Circuits, vol.35, pp1511-1514, Oct. 2000.
 5. C. Kun, S. Quan and A. Mason, "A power-optimized 64-bit priority encoder utilizing
parallel priority look-ahead," in Proceedings of the 2004 International Symposium on
Circuits and Systems, vol.2, pp. II753-6, 23-26 May, 2004.
 6. http://electronics-course.com/priority-encode

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