Chapter 4:

Combinational Circuits
 Output is function of input only
i.e. no feedback

Combinational
n inputs • • m outputs
•
• Circuits •
•


When input changes, output may change (after a delay)
 Combinational Circuits
 Analysis
● Given a circuit, find out its function ?
A
B
F1
C
A
B
C
A
B

?
● Function may be expressed as:
A
F2
C

B
C

♦ Boolean function
♦ Truth table

 Design
● Given a desired function, determine its circuit
● Function may be expressed as:
?
♦ Boolean function
♦ Truth table
 Design Procedure
 Given a problem statement:
● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit

Example:
Design a circuit to convert a “BCD” code to “Excess 3” code

 4-bits  4-bits
 0-9 values
?  Value+3
 Binary Adder
 Half Adder x S
y
HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0 C
y
 Binary Adder
 Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 0 0 0 0 0 1 0 1
C S
0 0 1 0 1 x 1 0 1 0
0 1 0 0 1 z
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
1 0 1 1 0 0 0 1 0
1 1 0 1 0 x 0 1 1 1
z
1 1 1 1 1 C = xy + xz + yz
 Binary Adder
 Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C z
z
y
z
 Binary Adder
 Full Adder
x S
y HA HA

z C

x
S

y
C

z
 Subtractors
 Half-Subtractor
 Full-Subtractor
 Half Subtractor

x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Full Subtractor ???

Design BCD to Excess-3 Code converter
 Design Procedure
 BCD-to-Excess 3 Converter
C C
A B C D w x y z
0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 1 0 0 1 1 1 1
B x x x x B
0 0 1 0 0 1 0 1 x x x x A
A 1 1 x x 1 x x
0 0 1 1 0 1 1 0 D
0 1 0 0 0 1 1 1
D
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x B x x x x B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
 Design Procedure
 BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
 Analysis Procedure
 Boolean Expression Approach
A
B
F1
C ABC
A A+B+C
B AB'C'+A'BC'+A'B'C
C
A
B (A’+B’)(A’+C’)(B’+C’)

A
F2
C
AB+AC+BC
B
C F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=0 0 0 0 0 0
0 0
B =0
F1
C =0
A =0
0 0
B =0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=0 0
0 0 0 0 0
B =0 1
F1 0 0 1 1 0
C =1
A =0
1 1
B =0
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=0 0
0 0 0 0 0
B =1 1
F1 0 0 1 1 0
C =0
0 1 0 1 0
A =0
1 1
B =1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=0 0
0 0 0 0 0
B =1 0
F1 0 0 1 1 0
C =1
A =0
0 1 0 1 0
1 0 0 1
B =1 0 1 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=1 0
0 0 0 0 0
B =0 1
F1 0 0 1 1 0
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0
1 1 0 0
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=1 0
0 0 0 0 0
B =0 0
F1 0 0 1 1 0
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 0 1 0 1 0 1
B =0

A =1 1 1
F2
C =1

B =0 0
C =1
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=1 0
0 0 0 0 0
B =1 0
F1 0 0 1 1 0
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0
0 1 0 0 1 0
A =1 1 1 0 1 0 1
B =1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0
 Analysis Procedure
 Truth Table Approach A B C F1 F2
A=1 1
0 0 0 0 0
B =1 1
F1 0 0 1 1 0
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 1 1 0 1 0 1
B =1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1 B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
 MULTILEVEL NAND CIRCUITS

 To show that any Boolean function can be implemented

with NAND gates we need to show that the logical
operations AND, OR, and NOT can be implemented with
NAND gates.
 Multilevel NAND & NOR circuits
 Two-level circuits consisting of AND and OR gates
can easily be converted to networks that can be
realized only NAND and NOR gates
 A two-level AND-OR (SOP) circuit can be realized
(directly) as a two-level NAND-NAND circuit
 A two-level OR-AND (POS) circuit can be realized
(directly) as a two-level NOR-NOR circuit
 The same approach can be used for multilevel
networks
 F=A(B+CD) + BC’

 F=(A+B’)(CD+E)
 MULTILEVEL NOR CIRCUITS
 F=A(B+CD)+BC’