PRESIDENCY UNIVERISTY, BENGALURU

School of Engineering

Department of Computer Science & Engineering

Microprocessors and Microcontroller

CSE 206

IV Semester 2019-20
Microprocessor & Microcontrollers
Course Outcomes

CO1: Describe the fundamental principles of 8086

Microprocessor and 8051 Microcontroller.

CO2: Apply the programming knowledge of 8086 and

8051 to write Assembly language Programs.

CO3: Explore interfacing of 8086 to I/O devices using

8255 Programmable Peripheral Interface.

3
Evaluation Components

Duration Weightage Marks Date &

Component Venue
(minutes) (%) (200M) Time

As per
Test1 & Test2 60 40 80 As per CoE
CoE 

Quiz + Flipped 20-Apr to

60 20 40 DGL3,4
Classroom 24-Apr

End Term As per

180 40 80 As per CoE
Examination CoE

4
Text Books

Text Book(s):
• T1: Douglas V. Hall & S.S.S.P. Rao, “Microprocessors and
Interfacing (SIE)”, 3rd ed., Mc Graw Hill, 2017.
• T2: Barry B Brey, “The Intel Microprocessors”, 8th edition,
Pearson, 2014.
Reference Book(s):
• R1: Muhammad Ali Mazidi, “Microprocessors and
Microcontrollers”, First Impression, Pearson Education.
• R2: Ramesh S. Gaonkar, “Microprocessor Architecture,
Programming, and Applications with the 8085”, 4e, Prentice
Hall, 1998

5
Module-1

• Introduction
• Organization of Computer Systems
• Architecture of Computers
• RISC and CISC
• Microprocessor Evolution
• Main Features of 8086
• 8086 Pin Diagram/Description
• 8086 Internal Architecture

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1.1 Organization of Computer Systems

• Components of a Computer
– Central Processing Unit
– Main Memory
– Secondary Memory
– I/O interfaces
Device
– Devices

Device
Main Memory
Controller

I/O Interface

CPU Device
Controller

Device

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1.1 Organization of Computer Systems

• Input is converted into standard 7 or 8 binary coded

characters and send to CPU
• CPU then sends this information to main memory
• Both data and program are stored in main memory and
performs the specified operations on the data
• BUS is used to connect the components
– Unidirectional
– Bidirectional

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1.2 Architecture of Computers

Definition of architecture
• Computer architecture is a specification detailing how a set
of software and hardware technology standards interact to
form a computer system or platform.
• In short, computer architecture refers to how a computer
system is designed and what technologies it is compatible
with.
2 types of architecture
– Von Neumann architecture
– Harvard architecture

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Von Neumann architecture

• John Von Neumann suggested that, data & programs

should be stored together in memory. This is now called Von
Neumann architecture.
• Hence this process being known as stored program concept

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Von Neumann architecture

• Now the question is how it differentiate data and

information?
• When information is fetched from the main memory
location address through a Program Counter(PC) register,
then that information is a machine instruction
• If the information is fetched with the address specified from
any other register, then that information is a data
• Drawback of Von Neumann architecture
• Channel bandwidth is finite
• Processor can go no faster when this channel
bandwidth is full
• This performance limiting factor is called Von
Neumann bottleneck

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Harvard architecture

• It has 2 memories-one for architecture & the other for data

• Increased bandwidth available due to separate buses for
instructions & data
• Disadvantage-storage is allocated to instructions & data in
a fixed ratio

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Instruction Set architecture

• The architecture of the Central Processing Unit (CPU) operates the

capacity to function from “Instruction Set Architecture” to where it
was designed.
• The architectural design of the CPU is Reduced instruction set
computing (RISC) and Complex instruction set computing (CISC).
• Reduced Set Instruction Set Architecture (RISC) –
The main idea behind is to make hardware simpler by using an
instruction set composed of a few basic steps for loading,
evaluating and storing operations just like a load command will
load data, store command will store the data.
• Complex Instruction Set Architecture (CISC) –
The main idea is to make hardware complex as a single instruction
will do all loading, evaluating and storing operations just like a
multiplication command will do stuff like loading data, evaluating
and storing it.
• Both approaches try to increase the CPU performance

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RISC and CISC

•RISC: Reduce the cycles per instruction at the cost of the

number of instructions per program.

•CISC: The CISC approach attempts to minimize the number of

instructions per program but at the cost of increase in number
of cycles per instruction.

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RISC and CISC

Complex Instruction Set Computer(CISC)

• Developed by Intel
• Main idea is to minimize number of instructions per
program, sacrificing number of cycles per instruction
• Computers based on CISC are designed to decrease the
memory cost
• Large programs need more storage, as memory size
increases it becomes expensive
• To solve these problems, number of instructions per
program can be reduced by embedding the number of
operations in a single instruction, thereby making the
instructions more complex

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RISC and CISC

Characteristics of CISC:-
1. Complex instruction, hence complex instruction decoding.
2. Instruction are larger than one word size.
3. Instruction may take more than single clock cycle to get
executed.
4. Less number of general purpose register as operation get
performed in memory itself.
5. Complex Addressing Modes.
6. More Data types.
Example – Suppose we have to add two 8-bit number:
CISC approach: There will be a single command or
instruction for this like ADD which will perform the task.

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RISC and CISC

Reduced Instruction Set Computer (RISC)

• RISC architecture is used in portable devices due to its
power efficiency (Apple iPod)
• Uses highly optimized set of instructions
• It reduces the cycles per instruction at the cost of the
number of instructions per program
• Pipelining is the unique feature of RISC
• Pipelining is performed by overlapping the execution of
several instructions in a pipeline fashion

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RISC and CISC

Characteristics of RISC:-
1. Simpler instruction, hence simple instruction decoding.
2. Instruction come under size of one word.
3. Instruction take single clock cycle to get executed.
4. More number of general purpose register.
5. Simple Addressing Modes.
6. Less Data types.
7. Pipelining can be achieved.
Example – Suppose we have to add two 8-bit number:
RISC approach: Here programmer will write first load command to
load data in registers then it will use suitable operator and then it
will store result in desired location.

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Difference between RISC and CISC

CISC RISC
• Focus on hardware • Focus on software
• Transistors are used for storing • Transistors are used for more
complex Instructions registers

• Code size is small • Code size is large

• Instruction take more than one • A instruction execute in single
clock cycle clock cycle

• Instruction are larger than size • A instruction fit in one word

of one word

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Microprocessor Evolution

• Microprocessor is a CPU on a single chip, consists of

millions of transistors & other electronic components that
process millions of instructions per second
• Microprocessor is a versatile chip, that is combined with
memory & special purpose chips & preprogrammed by a
software
• It accepts a digital data as input & process it according to
the instructions stored in the memory
• 1971
• First microprocessor, intel 4004 which is a 4 bit bus
• Speed was 60000 operations per second
• 2300 transistors based on 10-micron technology
• It can address 640 bytes
• It operates at 750 kHz

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Microprocessor Evolution

• 1972
• Intel introduces first 8 bit microprocessor intel 8008
• It can address 16K bytes of memory
• 3500 transistors were used based on 10 micron
technology
• Speed was 60000 operations per second
• 1974
• intel released its 2MHz 8080 chip, an 8 bity
microprocessor
• It can address 64K bytes of memory
• 6000 transistors were used based on 6 micron
technology
• Speed was 0.64 MIPS

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Microprocessor Evolution

• 1978
• Intel introduced 4.77 M Hz 8086 microprocessor.
• It has 16 bit registers, 16 bit data bus
• 29000 transistors were used based on 3 micron
technology
• It can address 1 M bytes of memory
• 1979
• Intel introduced 4.77 M Hz 8088 microprocessor.
• It operates on 16 bits internally, but supports 8 bit data
bits to use existing 8 bit devices
• 29000 transistors were used based on 3 micron
technology
• It can address 1 M bytes of memory
• Its speed is 0.33 M Hz

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Microprocessor Evolution

• 1985
• Intel introduced 6 M Hz 80286 microprocessor
• 134000 transistors were used based on 1.5 micron
technology
• Offers protected mode operation
• It can address 16 M bytes of memory or 1 GB of Virtual
memory
• Its speed is 0.9 M Hz
• 1989
• Intel announced 25 MHz 486 microprocessor
• It integrated the 386, 387 math coprocessor & added an
8 KB primary cache
• It used 1.2 million transistors based on 1 micron
technology
• Its speed is 20 MIPS

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Microprocessor Evolution

• 1991
• Intel introduced 50 MHz 486 microprocessor.
• Speed is 41 MIPS
• 1992
• Intel introduced 486 SL processor designed for
notebook computers.
• Speed is 20 MHz. It can address 64MB of physical
memory
• 1.4 million transistors were used based on 0.8 micron
technology
• 1993
• Intel introduced Pentium processor & used 32 bit
registers with a 64 bit data bus
• It can address 4GB of memory. Its speed was 60 MHz
• 3.1million transistors were used based on 0.8 micron
technology

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Microprocessor Evolution

• 1994
• Intel introduced 75 MHz Pentium processor. Speed was
126.5 MIPS.
• It uses 3.2 million transistors based on 0.6 micron
technology
• 1995
• Intel released Pentium pro which contained 5.5 million
transistors
• 1996
• Intel released 150 MHz mobile pentium processor
designed for use in portable computers
• 1997
• Intel released 7.7 million transistor Pentium II
processor
• 1999
• Intel released 450 MHz Pentium III processor. Its speed
was 450 to 1.15 GHz frequency
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Microprocessor Evolution

• 2000
• Intel released Pentium IV operating at 2GHz
• 2005
• Intel released its first desktop dual core processor called
Pentium D
• 291 million transistors were used at 3.2 GHz initial
speed.
• Present status
• Intel stops Pentium series and started Intel Core i3
series from 2012.
• As of June 2018, the lineup of core processors included
the Intel Core i9, Intel Core i7, Intel Core i5 and Intel
Core i3.

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8086 Microprocessor

27
8086 Microprocessor

Program controlled semiconductor device (IC-Integrated Circuit)

which fetches (from memory), decodes and executes instructions.

It is used as CPU (Central Processing Unit) in computers.

28
Main Features of 8086

• 16 bit processor
• 16 bit data bus
• 20 bit address bus
• Frequency range is 6-10 MHz
• Can do only fixed point arithmetic operations
• Along with coprocessor 8087, 8086 can do both fixed and
floating point operations
• It can operate in 2 modes
• Minimum
• Maximum

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Main Features of 8086

• It works in multiprocessor environment, control signals for

memory & I/O are generated by an external BUS controller
• It can pre-fetch up to 6 instructions from memory & queues
them in order to speed up the execution
• It requires +5V power supply
• It uses a 40 pin dual in line package
• 8086 has 2 blocks
• Bus Interfacing Unit (BIU)
• Execution Unit (EU)

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Pins and signals
8086 Microprocessor Pins and Signals Common signals

AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are multiplexed
with data.

When AD lines are used to transmit memory

address the symbol A is used instead of AD,
for example A0-A15.

When data are transmitted over AD lines the

symbol D is used in place of AD, for example
D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are
multiplexed with status signals

32
8086 Microprocessor Pins and Signals Common signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status
It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data
bus use BHE (Active Low) signal. It is
multiplexed with status signal S7.

MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.

It is active when low.

33
8086 Microprocessor Pins and Signals Common signals

  TEST
input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after execution of

the WAIT instruction and will resume execution
only when the is made low by an active
hardware.

This is used to synchronize an external activity

to the processor internal operation.

READY
This is the acknowledgement from the slow
device or memory that they have completed the
data transfer.

The signal made available by the devices is

synchronized by the 8284A clock generator to
provide ready input to the 8086.

The signal is active high.

34
8086 Microprocessor Pins and Signals Common signals

RESET (Input)
Causes the processor to immediately
terminate its present activity.
The signal must be active HIGH for at least
four clock cycles.

CLK
The clock input provides the basic timing
for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled
during the last clock cycles of each
instruction to determine the availability of
the request. If any interrupt request is
pending, the processor enters the interrupt
acknowledge cycle.
This signal is active high and internally
synchronized.

35
8086 Microprocessor Pins and Signals Min/ Max Pins

The 8086 microprocessor can work in

two modes of operations : Minimum
mode and Maximum mode.
In the minimum mode of operation the
microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can
work in multi-processor or co-processor
configuration.
Minimum or maximum mode operations
are decided by the pin MN/ MX(Active
low).
When this pin is high 8086 operates in
minimum mode otherwise it operates in
Maximum mode.

36
8086 Microprocessor Pins and Signals Minimum mode signals

  Pins 24 -31

For minimum mode operation, the MN/ is tied

to VCC (logic high)

8086 itself generates all the bus control signals

DT/: (Data Transmit/ Receive) Output signal
from the processor to control the direction of data
flow through the data transceivers
: (Data Enable) Output signal from the processor
used as out put enable for the transceivers
ALE: (Address Latch Enable) Used to demultiplex
the address and data lines using external latches
M/: Used to differentiate memory access and I/O
access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.
: Write control signal; asserted low Whenever
processor writes data to memory or I/O port
: (Interrupt Acknowledge) When the interrupt
request is accepted by the processor, the output is
low on this line.

37
8086 Microprocessor Pins and Signals Minimum mode signals

  Pins 24 -31
For minimum mode operation, the MN/
is tied to VCC (logic high)
8086 itself generates all the bus control
signals
HOLD: Input signal to the processor form
the bus masters as a request to grant the
control of the bus.
Usually used by the DMA controller to get
the control of the bus.
HLDA: (Hold Acknowledge) Acknowledge
signal by the processor to the bus master
requesting the control of the bus through
HOLD.
The acknowledge is asserted high, when the
processor accepts HOLD.

38
8086 Microprocessor Pins and Signals Maximum mode signals

  During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, , : Status signals; used by the 8086 bus controller

to generate bus timing and control signals. These are
decoded as shown.

39
8086 Microprocessor Pins and Signals Maximum mode signals

  During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, : (Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

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8086 Microprocessor Pins and Signals Maximum mode signals

  During maximum mode operation, the MN/ is

grounded (logic low)

Pins 24 -31 are reassigned

, :(Bus Request/ Bus Grant) These requests are

used by other local bus masters to force the
processor to release the local bus at the end of the
processor’s current bus cycle.

These pins are bidirectional.

The request on will have higher priority than

: An output signal activated by the LOCK prefix

instruction.

Remains active until the completion of the

instruction prefixed by LOCK.

The 8086 output low on the pin while executing an

instruction prefixed by LOCK to prevent other bus
masters from gaining control of the system bus.

41
Architecture
8086 Microprocessor Architecture

Bus Interface Unit (BIU)

BIU fetches instructions,
reads data from memory
and I/O ports, writes data
to memory and I/ O ports.

Execution Unit (EU)

EU executes instructions
that have already been
fetched by the BIU.

BIU and EU functions

separately.

43
8086 Microprocessor Architecture

Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

44
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access to

memory is divided address four segments (256 code and data in the
into segments of up K bytes within the 1 M byte segments by changing the
to 64K bytes each. of memory) at a particular segment register content
time. to point to the desired
segments.

45
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Segment Registers Code Segment Register

16-bit

CS contains the base or start of the current code

segment; IP contains the distance or offset from
this address to the next instruction byte to be
fetched.

BIU computes the 20-bit physical address by

logically shifting the contents of CS 4-bits to the
left and then adding the 16-bit contents of IP.

That is, all instructions of a program are relative

to the contents of the CS register multiplied by 16
and then offset is added provided by the IP.

46
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Segment Registers Data Segment Register

16-bit

Points to the current data segment; operands for

most instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) or

Destination Index (DI) or a 16-bit displacement are
used as offset for computing the 20-bit physical
address.

47
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Segment Registers Stack Segment Register

16-bit

Points to the current stack.

The 20-bit physical stack address is calculated

from the Stack Segment (SS) and the Stack
Pointer (SP) for stack instructions such as PUSH
and POP.

In based addressing mode, the 20-bit physical

stack address is calculated from the Stack
segment (SS) and the Base Pointer (BP).

48
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Segment Registers Extra Segment Register

16-bit

Points to the extra segment in which data (in

excess of 64K pointed to by the DS) is stored.

String instructions use the ES and DI to

determine the 20-bit physical address for the
destination.

49
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Segment Registers Instruction Pointer

16-bit

Always points to the next instruction to be

executed within the currently executing code
segment.

So, this register contains the 16-bit offset address

pointing to the next instruction code within the
64Kb of the code segment area.

Its content is automatically incremented as the

execution of the next instruction takes place.

50
8086 Microprocessor Architecture Bus Interface Unit (BIU)

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to 6
bytes of instruction code
are pre fetched from the
memory ahead of time.

This is done in order to

speed up the execution by
overlapping instruction
fetch with execution.

This mechanism is known

as pipelining.

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8086 Microprocessor Architecture Execution Unit (EU)

EU decodes and executes

instructions.

A decoder in the EU
control system translates
instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and

Index registers (Source Some of the 16 bit registers can be used as

Index, Destination Index) two 8 bit registers as :
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and DL 52
8086 Microprocessor Architecture Bus Interface Unit (BIU)

EU Registers Accumulator Register (AX)

Consists of two 8-bit registers AL and AH, which

can be combined together and used as a 16-bit
register AX.

AL in this case contains the low order byte of the

word, and AH contains the high-order byte.

The I/O instructions use the AX or AL for

inputting / outputting 16 or 8 bit data to or from
an I/O port.

Multiplication and Division instructions also use

the AX or AL.

53
8086 Microprocessor Architecture Bus Interface Unit (BIU)

EU Registers Base Register (BX)

Consists of two 8-bit registers BL and BH, which

can be combined together and used as a 16-bit
register BX.

BL in this case contains the low-order byte of the

word, and BH contains the high-order byte.

This is the only general purpose register whose

contents can be used for addressing the 8086
memory.

All memory references utilizing this register

content for addressing use DS as the default
segment register.

54
8086 Microprocessor Architecture Bus Interface Unit (BIU)

EU Registers Counter Register (CX)

Consists of two 8-bit registers CL and CH, which

can be combined together and used as a 16-bit
register CX.

When combined, CL register contains the low

order byte of the word, and CH contains the high-
order byte.

Instructions such as SHIFT, ROTATE and LOOP

use the contents of CX as a counter.

Example:

The instruction LOOP START automatically

decrements CX by 1 without affecting flags and will
check if [CX] = 0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

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8086 Microprocessor Architecture Bus Interface Unit (BIU)

EU Registers  Data Register (DX)

Consists of two 8-bit registers DL and DH, which

can be combined together and used as a 16-bit
register DX.

When combined, DL register contains the low

order byte of the word, and DH contains the high-
order byte.

Used to hold the high 16-bit result (data) in 16 X

16 multiplication or the high 16-bit dividend
(data) before a 32 16 division and the 16-bit
reminder after division.

56
8086 Microprocessor Architecture Bus Interface Unit (BIU)

EU Registers Stack Pointer (SP) and Base Pointer (BP)

SP and BP are used to access data in the stack

segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack
segment in the external memory.

SP contents are automatically updated

(incremented/ decremented) due to execution of a
POP or PUSH instruction.

BP contains an offset address in the current SS,

which is used by instructions utilizing the based
addressing mode.

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8086 Microprocessor Architecture Bus Interface Unit (BIU)

EU Registers Source Index (SI) and Destination Index

(DI)

Used in indexed addressing.

Instructions that process data strings use the SI

and DI registers together with DS and ES
respectively in order to distinguish between the
source and destination addresses.

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8086 Microprocessor Architecture Execution Unit (EU)

Flag Register

Auxiliary Carry
Flag Carry Flag

Undefined
Parity Flag

Sign Flag
Zero Flag

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U PF U CF

Over flow Flag Tarp Flag

Direction Flag
Interrupt Flag

59
8086 Microprocessor Architecture

8086 registers
categorized into 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

4 groups U U U U OF DF IF TF SF ZF U AF U PF U CF

Sl.No. Type Register width Name of register

16 bit AX, BX, CX, DX
1 General purpose register
8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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8086 Microprocessor Architecture Registers and Special Functions

Register Name of the Register Special Function

Stores the 16-bit results of arithmetic and
AX 16-bit Accumulator logic operations
8-bit Accumulator Stores the 8-bit results of arithmetic and logic
AL operations

Used to hold base value in base addressing

BX Base register mode to access memory data
Used to hold the count value in SHIFT,
CX Count Register ROTATE and LOOP instructions
Used to hold data for multiplication and
DX Data Register division operations
Used to hold the offset address of top stack
SP Stack Pointer memory
Used to hold the base value in base addressing
BP Base Pointer using SS register to access data from stack
memory
Used to hold index value of source operand
SI Source Index (data) for string instructions
Used to hold the index value of destination
DI Data Index operand (data) for string operations

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Thank You