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Arithmetic Circuits: Digital Electronics Bca Sem Ii Jims

The document discusses half adders, full adders, and full subtractors. A half adder adds two bits and produces a sum and carry output. A full adder adds three bits by incorporating the carry from a lower order addition. A full subtractor performs subtraction of three bits and produces difference and borrow out outputs. It uses two half subtractors internally to process the minuend, subtrahend, and borrow in bits.

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dinesh sharma
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77 views57 pages

Arithmetic Circuits: Digital Electronics Bca Sem Ii Jims

The document discusses half adders, full adders, and full subtractors. A half adder adds two bits and produces a sum and carry output. A full adder adds three bits by incorporating the carry from a lower order addition. A full subtractor performs subtraction of three bits and produces difference and borrow out outputs. It uses two half subtractors internally to process the minuend, subtrahend, and borrow in bits.

Uploaded by

dinesh sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Arithmetic Circuits

Digital Electronics
BCA Sem II
JIMS

1
Adders
– Half adder IS used to perform addition of two
bits .It has two inputs and 2 outputs

2
LOGIC SYMBOL

X SUM
HALF ADDER
Y CARRY

3
Half Adder
• S=XY
• C = XY
0
0

4
Half Adder
• S=XY
• C = XY
0 0
0

0
0
0

5
Half Adder
• S=XY
• C = XY
0
1

6
Half Adder
• S=XY
• C = XY
0 1
1

0
0
1

7
Half Adder
• S=XY
• C = XY
1
0

8
Half Adder
• S=XY
• C = XY
1 1
0

1
0
0

9
Half Adder
• S=XY
• C = XY
1 0
1

1
1
1

10
Half Adder
• S=XY
• C = XY
1 0
1

1
1
1

11
Half Subtractor

X Y D B
0 0 0 0
0 1 1 1 Half Subtractor is a
1 0 1 0 circuit that performs
1 1 0 0 subtraction of two
bits .It has 2 inputs and
produces two outputs
Half Subtractor

X Y D B X
D
0 0 0 0 Y
0 1 1 1
1 0 1 0
1 1 0 0
B

d=XY
B = X’Y
Half Subtractor is a circuit that performs subtraction
of two bits .It has 2 inputs and produces two outputs
LOGIC SYMBOL

difference
X
HALF subtractor
Y Borrow

14
Full Adder
• A half adder has only two inputs but there is no provision to add
carry from the lower order bits when multibit addition is performed .
A full adder is a combinational circuit that performs the sum of three
input bits and produces sum and carry

15
K MAP FOR SUM
XY
00 01 11 10
Z

0
0 1 0 1

0
1 1 0 1

16
K MAP FOR CARRY
XY
00 01 11 10
Z

0
0 0 1 0

1
1 0 1 1

17
Two Half Adders (and an OR)

HA HA

18
Case 1

0
0
0

0 0

19
Case 2

0
0
1 1

0
0 0

20
Case 3

1 1
1
0 1

1
0 0
0
0
0

21
Case 4

1 1
1
1 0

1
0 1
1
1
0

22
Case 5

1
1
0
1
0
1

0 1
0
0
0
0

23
Case 6

1
1
0
1
1
0

0 1 1
1
1
0

24
Case 7

1
0
1
0
0
0

1 0 0
0
1
1

25
Case 8

1
0
1
0
1
1

1 0
0
1
1
1

26
Full Subtractor

A B Borin D Borout

0 0 0 0 0
0 0 1 1 1 Full Subtractor is a combinational circuit
0 1 0 1 1 that performs subtraction involving three
bits namely minuend bit, subtrahend bit,
0 1 1 0 1 and borrow from previous stage.It has two
1 0 0 1 0 outputs
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K MAP FOR Borout
AB
00 01 11 10
Bor in

0
0 1 0 0 • A’B +A’Borin+BBorin
0
1 1 1 1

28
• D = A’B’Borin +A’BBorin’+AB’Borin’+ABBorin

• B = A’B +A’Borin+BBorin

29
Full Subtractor
CBor
i in

Ai Di
Bi HS HS

C out
Bor
i+1
Full Subtractor
CBor
i in

Ai Di
Bi

C out
Bor
i+1
Case 1: A :0 B:0 Borin : 0
0
CBor
i in

0 Ai 0 Di
0
0 Bi

1
0 1
0 0
0 0
C out
Bor
i+1

half subtractor
half subtractor
Case 2 : A :0 B:0 Borin : 1
1
CBor
i in

0 Ai 0 Di
1
0 Bi

1
0 1
0 1
1 1
C out
Bor
i+1

half subtractor
half subtractor
Case 3 : A :0 B:1 Borin : 0
0
CBor
i in

0 Ai 1 Di
1
1 Bi

1
1 0
1 0
0 1
C out
Bor
i+1

half subtractor
half subtractor
Case 4 : A :0 B:1 Borin : 1
1
CBor
i in

0 Ai 1 Di
0
1 Bi

1
1 0
1 0
1 1
C out
Bor
i+1

half subtractor
half subtractor
Case 5 : A :1 B:0 Borin : 0
0
CBor
i in

1 Ai 1 Di
1
0 Bi

0
0 0
0 0
0 0
C out
Bor
i+1

half subtractor
half subtractor
Case 6 : A :1 B:0 Borin : 1
1
CBor
i in

1 Ai 1 Di
0
0 Bi

0
0 0
0 0
1 0
C out
Bor
i+1

half subtractor
half subtractor
Case 7 : A :1 B:1 Borin : 0
0
CBor
i in

1 Ai 0 Di
0
1 Bi

0
0 1
1 0
0 0
C out
Bor
i+1

half subtractor
half subtractor
Case 8 : A :1 B:1 Borin : 1
1
CBor
i in

1 Ai 0 Di
1
1 Bi

0
0 1
1 1
1 1
Bor
C outi+1

half subtractor
half subtractor
1’s complement
• Rule: 1’s complement of a binary number
is formed by changing
– 1’s to 0’s
– 0’s to 1’s
• 1011000→0100111
• 0101101 →
2’s Complement
• Alternative Method
– Write the 1’s complement
– Add 1 to 1’s complement
• Example
– 1101100
– 0010011 (1’s complement)
– 0010100 (2’s complement)
Parallel Binary Adders:
To implement the addition of binary numbers, a full-adder
is required for each bit in the numbers.
So for 2-bit numbers, two adders are needed;
for 4-bit numbers, four adders are used; and so on.
The carry output of each adder is connected to the carry
input of the next higher-order adder
. Add two binary numbers 7 and 15 with previous carry
= 0.

So, 7 (decimal) = 0111 (in binary A4A3A2A1)


&    15 (decimal) = 1111 (in binary B4B3B2B1)
Parallel Adder

• To add two n-bit numbers together, n full-adders should be


cascaded.
Parallel Adder
0 1 1 1 1 1 1 1

0
Parallel Adder
0 1 1 1 1 1 1 1

0
Parallel Adder
0 1 1 1 1 1 1 1

1 0

1 1
1

0
Parallel Adder
0 1 1 1 1 1 1 1

1 1 0

1 1
1
1 1

0
Parallel Adder
0 1 1 1 1 1 1 1

1
1 1 0

1 1
1 1
1 1
0
0
4 bit Parallel Adder/Subtractor
• The 4 bit parallel adder/subtractor circuit performs
addition and subtraction. It has 2 4 bit inputs
A3A2A1A0 and B3B2B1B0.
• The control line M is connected with C0 of the least
significant bit of the full adder, is used to perform
addition/ subtraction.
• To perform subtraction , M is kept high (i.e M =1) . The
Ex OR gates output the 1’s complement of
B3B2B1B0.Since a 1 is given to C0 of the LSB of full
adder , it is added to the 1’s complement of
B3B2B1B0, yielding the 2’s complement of B3B2B1B0
producing Sum S3S2S1S0 which is actually the
Difference and Carry which is the borrow

49
4 bit Parallel Adder/Subtractor
• To perform addition M=0, B3B2B1B0 is
applied directly to the inputs of full adders
and added with A3A2A1A0 yielding Sum
S3S2S1S0 and carry

50
4-bit Adder-Subtractor
M =0 : Adder B  M + C = B  0 + 0 = B,  A + B
M =1 : Subtractor B  M + C = B  1 + 1 = B’ + 1= -B(2’s comp), A - B

B3 A3 B2 A2 B1 A1 B0 A0

C4 C0
FA FA FA FA

S3 S2 S1 S0

51
4-bit Adder-Subtractor
M =0 : Adder
Let A = 1000 and Let B = 0001

B3 A3 B2 A2 B1 A1 B0 A0

C4 C0
FA FA FA FA

S3 S2 S1 S0

52
4-bit Binary Adder-Subtractor
M =0 : Adder
Let A = 1000 and Let B = 0001

B3 :0 A3:1 B2:0 A2:0 B1: 0 A1: 0 B0 :1 A0: 0

M=0 M=0 M=0 M=0

0 0 1 M=0
0
C4 C0
FA FA FA FA

S3 S2 S1 S0

53
4-bit Binary Adder-Subtractor
M =0 : Adder
Let A = 1000 and Let B = 0001
1000 +0001 + 0 = 1001, C4 =0

1 0 0 0

0 0 1
0
0 C0
FA FA FA FA

C4
1 0 0 1
0

54
4-bit Binary Adder- Subtractor
M =1 : Subtractor
Let A = 1000 and Let B = 0001

B3 A3 B2 A2 B1 A1 B0 A0

C4 C0
FA FA FA FA

S3 S2 S1 S0

55
4-bit Binary Adder-Subtractor
M =1 : Subtractor
Let A = 1000 and Let B = 0001

0 1 0 0 0 0 1 0

1 1 1 1

1 1 0 1
1
C4 C0
FA FA FA FA

S3 S2 S1 S0
Notice that after B + 1 , we get the 1’s complement of B, since M is
also the input for the carry C0---------------------
, 1 is propagated as carry input 56
Shweta-----------------------------------
through each FA, yielding the 2’s complement of B
4-bit Binary Adder-Subtractor
M =1 : Subtractor
Let A = 1000 and Let B = 0001
1000 + 1110 + 1= 1000 + 1111 = 0111, c4 =1

1 0 0 0

1 1 0 1
1
C0
FA FA FA FA

1
C4
0 1 1 1
Notice that after B + 1 , we get the 1’s complement of B, since M is
also the input for the carry C0---------------------
, 1 is propagated as carry input 57
Shweta-----------------------------------
through each FA, yielding the 2’s complement of B

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