3 Dataflow-Modelling
3 Dataflow-Modelling
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Dataflow Verilog Modeling
A dataflow description is based on function rather than structure.
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Continuous Assignment
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Rules
The left hand side of an assignment must always be a scalar or vector net
It cannot be a scalar or vector register.
Delay values can be specified for assignments in terms of time units. Delay values
are used to control the time when a net is assigned the evaluated value
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Dataflow Modeling (cont.)
Delay can be introduced
Example: assign #2 sum = a ^ b;
“#2” indicates 2 time-units
No delay specified : 0 (default)
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4-1 Multiplexer
// 4-to-1 Line Multiplexer: Dataflow Verilog Description (Boolean)
module multiplexer_4_to_1_df_v(S, I, Y);
input [1:0] S;
input [3:0] I;
output Y;
assign Y = (~ S[1] & ~ S[0] & I[0])| (~ S[1] & S[0] & I[1])
| (S[1] & ~ S[0] & I[2]) | (S[1] & S[0] & I[3]);
endmodule
Decoder example
module dec2_4 (a,b,en,y0,y1,y2,y3)
input a, b, en;
output y0,y1,y2,y3;
assign y0= (~a) & (~b) & en;
assign y1= (~a) & b & en;
assign y2= a & (~ b) & en;
assign y3= a & b & en;
end module
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“
Thankyou
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