BEHAVIOR

MODELLING
REVIEW
 Different level of abstractions
 Gate-level modeling
 Netlist of gates
 Dataflow modeling
 Boolean function assigned to a net
 Now, behavioral modeling
 A sequential algorithm (quite similar to software) that
determines the value(s) of signal(s)

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DATAFLOW VS PROCEDURAL
(BEHAVIORAL)
Procedural Dataflow
reg [3:0] Q; wire [3:0]Q;
wire [1:0] y; wire [1:0]y;
assign
always@(y)
Q[0]=(~y[1])&(~y[0]),
begin Q[1]=(~y[1])&y[0],
Q=4’b0000; Q[2]=y[1]&(~y[0]),
case(y) begin Q[3]=y[1]&y[0];
2’b00: Q[0]=1;
2’b01: Q[1]=1; Q[0]

2’b10: Q[2]=1;
Q[1]

2’b11: Q[3]=1; y[0] Q[0]

You don’t Q[2]
endcase have to Q[1]
y[1] work out Q[2] y[0]
end logic Q[3]
Q[3] y[1]

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 DATAFLOW VS
BEHAVIORAL
Dataflow Behavioral

 Describes the flow of data  Models how circuit behaves to

through the circuit inputs (No implementation details)

 Concurrent assignment  Sequential assignment

 Order does not matter  Order of statements are important.

 Starts with assign statements  Starts with initial or always

statement
 Useful for small and Simple
 Easy to code
circuits
wire c, d; reg c, d;
assign c =a & b; always@ (a or b or c)
assign d = c |b; begin
c =a & b;
d = c |b;
end
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 INTRODUCTION
 Represents circuits at functional and algorithmic level.
 Use proceedural statements similar in concept to
proceedural programming languages (e.g. C, Java),
 Behavioural modelling is mostly used to represent
sequential circuits.
 Behavioural models place proceedural statements in a
block after the always keyword.
 The always keyword takes a list of variables. The
block of statements is executed whenever one of the
variables changes.
 The target variables are of type reg. This type retains
its value until a new value is assigned.
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STRUCTURED PROCEDURES
 Two basic structured procedure
statements
always
initial
 All behavioral statements can appear only
inside these blocks
 Each always or initial block has a separate
activity flow (concurrency)
 Start from simulation time 0
 Cannot be nested

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BEHAVIORAL MODELING
 Procedural blocks:
 initial block: executes only once
 always block:executes in a loop
 Block execution is triggered based on user-
specified conditions
 always @ (posedge clk) ………
 All procedural blocks are automatically activated
at time 0
 All procedural blocks are executed concurrently
 reg is the main data type that is manipulated
within a sequential block
 It holds its value until assigned a new value
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INITIAL AND ALWAYS
 Initial blocks execute once
 at t = 0
 Always blocks execute continuously
 at t = 0 and repeatedly thereafter

initial always
begin begin

• •
• •
• •

end end

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STRUCTURED PROCEDURES:
INITIAL STATEMENT
 Starts at time 0
 Executes only once during a simulation
 Multiple initial blocks, execute in
parallel
 All start at time 0
 Each finishes independently

 Syntax:
initial
begin
// behavioral statements
end
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 INITIAL STATEMENT
 Executes only once at the beginning of simulation

initial
statements
 Used for initialization and waveform generation

//Initialization:
reg [7:0] RAM[0:1023];
reg RIB_REG;

initial begin
group
integer INX;
multiple RIB_REG =0;
statements for (INX = 0; INX < 1024; INX = INX + 1)
RAM[INX] = 0;
end
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INITIAL STATEMENT
(CONT’D)
 Example:
module stimulus;
reg x, y, a, b, m; initial
#50 $finish;
initial
m= 1’b0;
endmodule

initial
begin
#5 a=1’b1;
#25 b=1’b0;
end

initial
begin
#10 x=1’b0;
#25 y=1’b1;
end

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 ALWAYS STATEMENT
 Executes continuously; must be used with some form of timing control
always (timing_control) always
statements CLK = ~CLK
// Will loop indefinitely
 Four forms of event expressions are often used
 An OR of several identifiers (comb/seq logic)
 The rising edge of a identifier (for clock signal of a register)
 The falling edge of a identifier (for clock signal of a register)
 Delay control (for waveform generator)
 Any number of initial and always statements may appear
within a module
 Initial and always statements are all executed in parallel pp.
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 ALWAYS STATEMENT
module example (D, CURRENT_STATE, Q, NEXT_STATE);
input D, CURRENT_STATE;
output Q, NEXT_STATE;
reg CLK, Q, NEXT_STATE; delay-controlled always block
clock period = 10
always #5 CLK = ~CLK;

activated when CLK has

always @(posedge CLK)
a 0 -> 1 transition
begin
Q =D;
activated when CLK has
end
always @(negedge CLK) a 1 -> 0 transition
begin
NEXT_STATE = CURRENT_STATE;
end
endmodule

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 ALWAYS STATEMENT
 Start at time 0
 Execute the statements in a looping fashion
 Example
module clock_gen;
reg clock;

// Initialize clock at time zero

initial Can we move this
clock = 1’b0; to the always
block?
// Toggle clock every half-cycle (time period =20)
always
#10 clock = ~clock;

initial What happens if such

#1000 $finish; a $finish is not
endmodule included? 14
INITIAL AND ALWAYS BLOCKS
COMPARISON
 Basic components for behavioral modeling

always
initial
begin
begin
… imperative statements …
… imperative statements …
end
end
• Runs when simulation starts
• Runs when simulation starts
• Restarts when control
• Terminates when control
reaches the end
reaches the end
• Good for modeling/specifying
• Good for providing stimulus
hardware

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 PROCEDURAL
ASSIGNMENTS
 Assignments inside initial and always
 Are used to update values of reg, integer, real, or time
variables
 The value remains unchanged until another procedural
assignment updates it
 In contrast to continuous assignment (Dataflow Modeling,
previous chapter)

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 CONT’D..
 Syntax
 <lvalue> = <expression>

 <lvalue> can be
 reg, integer, real, time
 A bit-select of the above (e.g., addr[0])
 A part-select of the above (e.g., addr[31:16])
 A concatenation of any of the above
 <expression> is the same as introduced in dataflow modeling
 What happens if the widths do not match? (Already discussed)
 LHS wider than RHS => RHS is zero-extended
 RHS wider than LHS => RHS is truncated (Least significant part is
kept)

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PROCEDURAL ASSIGNMENT
 Inside an initial or always block:
sum = a + b + cin;

 Just like in C: RHS evaluated and assigned to LHS before

next statement executes

 RHS may contain wires and regs

 Two possible sources for data

 LHS must be a reg

 Primitives or cont. assignment may set wire values

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BLOCKING VS. NON-BLOCKING
ASSIGNMENT

Regs is procedural blocks can be defined with blocking or non-

blocking assignment.
Use non-blocking for flops and blocking for combinatorial.
always @(posedge CLK)
begin
if (reset) Q <= 0;
else Q <= D;
end
always @(A or B or Sel)
begin
if (Sel) Z = A;
else Z = B;
end
THE D FLIP-FLOP

module DFF(in, clk, clrn, out, outn);

input in, clk, clrn;
output out, outn;

wire in, clk, clrn;

reg out, outn;

always @(posedge clk or negedge clrn) begin

if (~clrn) begin
out <= 0;
outn <= 1;
end
else begin
out <= in;
outn <= ~in;
end
end
endmodule

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VERILOG PROCEDURAL
CONSTRUCTS
 If-then-else statement
 case statement
 for loop (not used often in synthesizable code)
 while loop (not used often in synthesizable code)
BEHAVIORAL MODELING STATEMENTS:
CONDITIONAL STATEMENTS
 Just the same as if-else in C
 Syntax:
if (<expression>) true_statement;

if (<expression>) true_statement;
else false_statement;

if (<expression>) true_statement1;
else if (<expression>) true_statement2;
else if (<expression>) true_statement3;
else default_statement;

 True is 1 or non-zero
 False is 0 or ambiguous (x or z)
 More than one statement: begin end
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CONDITIONAL STATEMENTS
( CONT’D )
 Examples:
if (!lock) buffer = data;

if (enable) out = in;

if (number_queued < MAX_Q_DEPTH)

begin
data_queue = data;
number_queued = number_queued +1;
end
else $display(“Queue full! Try again.”);

if (alu_control==0)
y = x+z;
else if (alu_control==1)
y = x-z;
else if (alu_control==2)
y = x*z;
else
$display(“Invalid ALU control signal.”);

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 VERILOG IF EXAMPLE
 Same as C if statement

// Simple 4:1 mux

module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
if (sel == 2’b00) Y = A;
else if (sel == 2’b01) Y = B;
else if (sel == 2’b10) Y = C;
else if (sel == 2’b11) Y = D;

endmodule
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VERILOG IF
 Another way

// Simple 4:1 mux

module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
if (sel[0] == 0)
if (sel[1] == 0) Y = A;
else Y = B;
else
if (sel[1] == 0) Y = C;
else Y = D;
endmodule
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BEHAVIORAL MODELING STATEMENTS:
MULTIWAY BRANCHING

 Similar to switch-case statement in C

 Syntax:
case (<expression>)
alternative1: statement1;
alternative2: statement2;
...
default: default_statement; // optional
endcase
 Notes:
 <expression> is compared to the alternatives in the
order specified.
 Default statement is optional

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MULTIWAY BRANCHING (CONT’D)
 Examples:

reg [1:0] alu_control;

...
case (alu_control)
2’d0: y = x + z;
2’d1: y = x – z;
2’d2: y = x * z;
default: $display(“Invalid ALU control signal.”);

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MULTIWAY BRANCHING (CONT’D)

 Example 2:
module mux4_to_1(out, i0, i1, i2, i3, s1, s0);
output out;
input i0, i1, i2, i3, s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1,s0})
2’d0: out = i0;
2’d1: out = i1;
2’d2: out = i2;
2’d3: out = i3;
endcase
endmodule

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 MULTIWAY BRANCHING
(CONT’D)
 The case statements compares <expression> and
alternatives bit-for-bit
 x and z values should match

module demultiplexer1_to_4(out0, out1, out2, out3, in, s1,

s0);
output out0, out1, out2, out3;
input in, s1, s0;
always @(s1 or s0 or in)
case( {s1, s0} )
2’b00: begin ... end
2’b01: begin ... end
2’b10: begin ... end
2’b11: begin ... end
2’bx0, 2’bx1, 2’bxz, 2’bxx, 2’b0x, 2’b1x, 2’bzx:
begin ... end
2’bz0, 2’bz1, 2’bzz, 2’b0z, 2’b1z:
begin ... end
default: $display(“Unspecified control signals”);
endcase
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endmodule
 VERILOG CASE
 Sequential execution of cases
 Only first case that matches is executed (implicit break)
 Default case can be used

// Simple 4-1 mux

module mux4 (sel, A, B, C, D, Y);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment

always @(sel or A or B or C or D)
case (sel)
2’b00: Y = A;
2’b01: Y = B;
Conditions tested in
2’b10: Y = C;
top to bottom order
2’b11: Y = D;
endcase
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endmodule
CASEX AND CASEZ

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 VERILOG CASE
 Note:
case (case_expression)
case_item1 : case_item_statement1;
case_item2 : case_item_statement2;
case_item3 : case_item_statement3;
case_item4 : case_item_statement4;
default : case_item_statement5;
endcase

 … is the same as …
if(case_expression == case_item1)
case_item_statement1;
else if (case_expression == case_item2)
case_item_statement2;
else if (case_expression == case_item3)
case_item_statement3;
else if (case_expression == case_item4)
case_item_statement4;
else case_item_statement5; 32
VERILOG CASE
 Without the default case, this example would create a latch for Y
 Assigning X to a variable means synthesis is free to assign any value

// Simple binary encoder (input is 1-hot)

module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (A)
8’b00000001: Y = 0;
8’b00000010: Y = 1;
8’b00000100: Y = 2;
8’b00001000: Y = 3;
8’b00010000: Y = 4;
8’b00100000: Y = 5;
8’b01000000: Y = 6;
8’b10000000: Y = 7;
default: Y = 3’bXXX; // Don’t care when input is not
hot 33
endcase
 VERILOG CASE (CONT)
 Cases are executed sequentially
 Following implements a priority encoder

// Priority encoder
module encode (A, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
reg [2:0] Y; // target of assignment

always @(A)
case (1’b1)
A[0]: Y = 0;
A[1]: Y = 1;
A[2]: Y = 2;
A[3]: Y = 3;
A[4]: Y = 4;
A[5]: Y = 5;
A[6]: Y = 6;
A[7]: Y = 7;
default: Y = 3’bXXX;// Don’t care when input
is all 0’s
endcase
endmodule 34
CASEX EXAMPLE
// Priority encoder
module encode (A, valid, Y);
input [7:0] A; // 8-bit input vector
output [2:0] Y; // 3-bit encoded output
output valid; // Asserted when an input is not all 0’s
reg [2:0] Y; // target of assignment
reg valid;

always @(A) begin

valid = 1;
casex (A)
8’bXXXXXXX1: Y = 0;
8’bXXXXXX10: Y = 1;
8’bXXXXX100: Y = 2;
8’bXXXX1000: Y = 3;
8’bXXX10000: Y = 4;
8’bXX100000: Y = 5;
8’bX1000000: Y = 6;
8’b10000000: Y = 7;
default: begin
valid = 0;
Y = 3’bX; // Don’t care when input is all 0’s
end
endcase
end
endmodule
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WHILE LOOPS
 A increasing sequence of values on an
output

reg [3:0] i, output;

intial begin
i = 0;
while (I <= 15) begin
output = i;
#10 i = i + 1;
end
end

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LOOPING STATEMENTS:
WHILE

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REPEAT LOOP
 Executes the following statement a fixed number of
times.
 Example:
repeat(100) $display(“I will not chew gum in class!”);

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FOR LOOP
 Executes code as long as the specified
condition is true
 Sets up initial conditions and conditions to
be executed on each loop
 Example:
// execute code while count < 10
for (count = 0; count < 10; count = count + 1) begin
$display(“Count = %0d”, count);
#10;
end

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FUNCTIONS AND TASKS
 Small sections of frequently used code.
 Tasks
 Can contain any kind of code and any number of
inputs and outputs.
 Can contain delays

 Functions
 Cannot include any delay information.
 Executed in zero time (simulation time).
 Must have at least one input
 Must have exactly one output.

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FUNCTIONS
module test_module;
reg [7:0] input;
reg [7:0] filter;
reg output;
...
output = test_function(input, filter);
...
function test_function; // this is the function declaration
input [7:0] data; // these are the inputs
input [7:0] mask;
reg temp; // this is an internal register
begin // begin the function logic
temp = data & mask;
if (temp > 16)
test_function = 1; // this is the output
else
test_function = 0; // this is the output
end
endfunction
endmodule
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TASKS
module test_module;
reg [7:0] input;
reg out1;
reg [7:0] out2;
test_task(input, out1, out2);
...
task test_task; // this is the task declaration
input [7:0] in_data; // these are the inputs
output out_data1;// these are the outputs
output [7:0] out_data2;
out_data1 = #3 ^in_data;
out_data2 = #2 in_data & 8’h7E;
endtask

endmodule

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BEHAVIORAL DESCRIPTION OF 2-
INPUT MUX
module mux2x1_bh(A,B,select,OUT);
input A,B,select;
output OUT;
reg OUT;
always @ (select or A or B)
if (select == 1) OUT = A;
else OUT = B;
endmodule
 BLOCKING ASSIGNMENTS

 BLO
NON BLOCKING
ASSIGNMENTS
SIMULATION QUEUES
SEQUENTIAL PROCEDURAL ASSIGNMENTS
CONCURRENT PROCEDURAL ASSIGNMENTS
THANK
YOU

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