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Direct Memory Access

This document discusses Direct Memory Access (DMA). It defines DMA as the transfer of data between memory and peripheral devices without involving the CPU. It describes the hardware components that enable DMA, including the DMA controller, address buffer, data buffer, and data counter. It explains how the DMA controller requests and is granted access to the memory bus to directly transfer blocks of data between memory and I/O devices, freeing up the CPU to perform other tasks.

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60 views19 pages

Direct Memory Access

This document discusses Direct Memory Access (DMA). It defines DMA as the transfer of data between memory and peripheral devices without involving the CPU. It describes the hardware components that enable DMA, including the DMA controller, address buffer, data buffer, and data counter. It explains how the DMA controller requests and is granted access to the memory bus to directly transfer blocks of data between memory and I/O devices, freeing up the CPU to perform other tasks.

Uploaded by

ayan dey
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Direct Memory Access

Presented by:

SANDIP
DOLAI
Overview
 Definitions
 How it works?
 Hardware components for DMA
 Working of components
 Procedure
 Cycle Stealing
 DMA select & register select
 Read and write
 Bus request & Bus grant
 Basic Concepts
 DMA controller
 Internal Architecture
 References
Definitions…
 Transfer of data under programmed I/O
is between CPU & peripheral devices.

 An interface to transfer the data in & out


memory through memory bus.
How It Works?

 The CPU initiates the transfer by applying the interface with


the starting address & the no. of words needed to be
transferred & then proceeds to execute some other tasks.

 Before transferring the data DMA requests the memory bus.

 If the request is granted, DMA transfers the data directly


into memory.
Hardware Components for DMA…

 DMA Controller – A special interface circuit to


control the DMA operation.

 IODR (Data Buffer Register) .

 IOAR (Address Buffer Register) .

 DC (Data Count Register).


Workings of Components…
 IOAR stores the adress of the next word to be
transferred. It is incremented / decremented
automatically after each word transfer.

 DC (Data Counter) stores the no. of words that


remain to be transferred. It is decremented
automatically after each word transfer. If DC=0 DMA
transfer halts.

 It has a interrupt capability, to signal the CPU the


I/O data transfer.
Procedures…
 In a DMA block transfer an arbitrary length
data word sequence is transferred in a single
burst while the DMA controller is master of
the memory bus.
 Block DMA transfer supports the fastest I/O
data transfer but it can make the CPU inactive
for relatively long periods by keeping the
system bus.
Cycle Stealing

Allows the controller to use the system bus to transfer


one data word. After which it must return control of
the bus to the CPU.Consequently a long blocks of I/O
data are transferred by a sequence of DMA bus
transaction interleaved with CPU bus transfer
transaction

Cycle stealing reduces the maximum I/O transfer rate.


It also reduces the interference by the DMA controller
in the CPU’s memory access.
Transparent DMA

 It is possible to eliminate this


interference completely by designing
the DMA interface so that bus cycles
are stolen only when the CPU is not
actually using the system bus - is
called transparent DMA.
DMA SELECT & REGISTER SELECT
 To the CPU ,the DMA controller is just like another I/O
device. Multiple DMA controller may be present in a
system each serving number of I/O device. So, for a
particular DMA controller to be activated when needed,
CPU service is needed i.e CPU must select it to make the
controller active via the DMA select input.

 CPU selects the register in the dma controller by enabling


the register select input.
READ & WRITE
 Through these 2 bidirectional lines, CPU
communicates with the DMA registers
through the data bus with the help of read-
write lines. CPU writes the starting address of
the memory location, no of words to be
transferred in the DMA registers through the
‘write’ line. Also CPU reads the status of the
transfer through the ‘read’ line.
BUS REQUEST & BUS GRANT
 CPU controlles the buses like a master & other units acts as bus
slaves. But in case of DMA, where transfer occur directly between
memory & I/O device under control of DMA with out direct
intervention of CPU.

 The Bus control goes to the DMA controller & not to the CPU. So
when a DMA controller is ready for a DMA transfer, It requests the
CPU to release the bus controls through the ‘bus request’ line by
enabling it.

 On getting the request from the DMA controller to release the


bus, CPU enables the ’bus grant’ line to let the controller no that
the CPU has released the bus & the controller can carry on with
the DMA transfer.
Basic Concepts…
 The basic idea of DMA is to transfer blocks of data
directly between memory & peripherals. The data
don’t go through the microprocessor but the data
bus is occupied.
 “Normal” transfer of one data byte takes up to 29
clock cycles.
 The DMA transfer requires only 5 clock cycles.
Nowadays, DMA can transfer data as fast as 60 Mbps.
The transfer rate is limited by the speed of memory
and peripheral devices.
DMA controller

A DMA controller interfaces with several peripherals that


may request DMA.

The controller decides the priority of simultaneous DMA


requests communicates with the peripheral & the CPU,
& provides memory addresses for data transfer.

DMA controller commonly used with 8088 is the 8237


programmable device.
 DMA controller
Internal Architecture

Main Memory

DC IOAR IODR
CPU

Control Unit
References

http://en.wikipedia.org/wiki/Direct_memory_access

Computer System Architecture by M. Morris Mano

http://cires.colorado.edu/jimenez-
group/QAMSResources/Docs/DMAFundamentals.pdf

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