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Communication Engineering 1
 Digital circuit design has evolved rapidly over the last
25 years.
 The earliest digital circuits were designed with vacuum

tubes and transistors. Integrated

 circuits were then invented where logic gates were

placed on a single chip.

 SSI (Small scale integration)
 MSI (Medium Scale Integration)
 LSI (Large Scale Integration)

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 Design processes started getting very complicated, and
designers felt the need to automate these processes.

 Chip designers began to use circuit and logic

simulation techniques to verify the functionality of
building blocks.

 VLSI (Very Large Scale Integration) designers could

design single chips with more than 100,000 transistors.

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 Computer-aided techniques became critical for
verification and design of VLSI digital circuits

 Logic simulators came into existence to verify the

functionality of these circuits before they were
fabricated on chip

 Designers could iron out functional bugs in the

architecture before the chip was designed further

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Communication Engineering 4
 HDLs allowed the designers to model the concurrency of
processes found in hardware elements.

 Hardware description languages such as Verilog HDL and

VHDL became popular.

 Verilog HDL originated in 1983 at Gateway Design

Automation.

 Both verilog and VHDL simulators to simulate large digital

circuits quickly gained acceptance from designers.

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 The advent of logic synthesis in the late 1980s changed the
design methodology radically.

 Digital circuits could be described at a register transfer level

(RTL) by use of an HDL.

 The details of gates and their interconnections to implement

the circuit were automatically extracted by logic synthesis
tools from the RTL description.

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 HDLs were used for simulation of system boards,
interconnect buses, FPGAs (Field Programmable Gate
Arrays), and PALS (Programmable Array Logic).

 A common approach is to design each IC chip, using

an HDL, and then verify system functionality via
simulation.

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Communication Engineering 7
Basic Design Methodology

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 Modeling Digital Systems
• Verilog HDL is for writing models of a system
• Reasons for modeling
– requirements specification
– documentation
– testing using simulation
– formal verification
– synthesis
• Goal
– most reliable design process, with minimum cost
and time
– avoid design errors! School of Electronics and
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Domains and Levels of Modeling

Structural Functional

High level of
abstraction

Low level of
abstraction

“Y-chart” due to
Gajski & Kahn
Geometric
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Communication Engineering 10
Domains and Levels of Modeling

Structural Functional
Algorithm
(behavioral)

Register-Transfer
Language

Boolean Equation

Differential Equation

“Y-chart” due to
Geometric Gajski & Kahn

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 Domains and Levels of Modeling

Structural Functional
Processor-Memory
Switch

Register-Transfer

Gate

Transistor

“Y-chart” due to
Gajski & Kahn
Geometric
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Communication Engineering 12
Domains and Levels of Modeling

Structural Functional

Polygons

Sticks

Standard Cells

Floor Plan

Geometric “Y-chart” due to

School ofGajski
Electronics&
andKahn
Communication Engineering 13
Two Modeling Hardware Description
Languages

VHDL and Verilog

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 Verifying Logic
 Phil Moorby from Gateway Design Automation in 1984 to
1987 (absorbed by Cadence)
 Verilog-XL Simulator from GDA in 1986
 Synopsys synthesis tool in 1988
 In 1990 became open language, OVI (Open Verilog
International)
 IEEE standard 1995
 Similar to C
 Fairly efficient and easy to write
 Case sensitive

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 Verilog Hardware Description Language(HDL)?
◦ A high-level computer language can model, represent
and simulate digital design
 Hardware concurrency
 Parallel Activity Flow
 Semantics for Signal Value and Time

◦ Design examples using Verilog HDL

 Intel Pentium, AMD K5, K6, Atheon, ARM7, etc
 Thousands of ASIC designs using Verilog HDL

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 Verilog is similar to c- language.

 VHDL is similar to Ada- (Ada is a structured, statically

typed, imperative, wide-spectrum, and object-oriented
high-level computer programming language, extended
from Pascal )

 Many feel that Verilog is easier to learn and use than

VHDL.

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 Gateway Design Automation
◦ Phil Moorby in 1984 and 1985

 Verilog-XL, "XL algorithm", 1986

◦ a very efficient method for doing gate-level simulation

 Verilog logic synthesizer, Synopsys, 1988

◦ the top-down design methodology is feasible

 Cadence Design Systems acquired Gateway

◦ December 1989
◦ a proprietary HDL

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 Open Verilog International (OVI), 1991
◦ Language Reference Manual (LRM)
◦ making the language specification as vendor-independent as
possible.

 The IEEE 1364 working group, 1994

◦ to turn the OVI LRM into an IEEE standard.

 Verilog became an IEEE standard

◦ December, 1995.

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FPGA Design Advantages

 Faster time-to -market:

No layout, masks or other manufacturing steps are needed for
FPGA design. Readymade FPGA is available and burn your HDL
code to FPGA!

 Simpler design cycle:

This is due to software that handles much of the routing, placement,
and timing. Manual intervention is less.The FPGA design flow
eliminates the complex and time-consuming floorplanning, place
and route, timing analysis.
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 More predictable project cycle:
The FPGA design flow eliminates potential re-spins,
wafer capacities, etc of the project since the design
logic is already synthesized and verified in FPGA
device.

 Field Reprogramability:
A new bitstream ( i.e. your program) can be uploaded
remotely, instantly. FPGA can be reprogrammed . But
not possible with ASIC.
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 Reusability:
Prototype of the design can be implemented on FPGA
which could be verified for almost accurate results so
that it can be implemented on an ASIC.

 If design has faults change the HDL code, generate bit

stream, program to FPGA and test again.Modern
FPGAs are reconfigurable both partially and
dynamically.

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FPGA Design Disadvantages:
 Power consumption in FPGA is more. You don't have any
control over the power optimization. This is where ASIC
wins the race !

 You have to use the resources available in the FPGA. Thus

FPGA limits the design size.

 Good for low quantity production. As quantity increases cost

per product increases compared to the ASIC
implementation.
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 ASIC Design Advantages:
 Lower unit costs: For very high volume designs costs comes
out to be very less. Larger volumes of ASIC design proves to be cheaper
than implementing design using FPGA.

 Speed:ASICs are faster than FPGA:

ASIC gives design flexibility. This gives enormous opportunity for
speed optimizations

 Low power:
ASIC can be optimized for required low power. There are several low
power techniques such as power gating, clock gating, cell libraries,
pipelining etc are available to achieve the power target.

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 ASIC Design Disadvantages
 Time-to-market:
 Some large ASICs can take a year or more to design. A good way to
shorten development time is to make prototypes using FPGAs and then
switch to an ASIC.
 Design Issues:
 In ASIC you should take care of Signal Integrity issues and many more.
In FPGA you don't have all these because ASIC designer takes care of
all these.

 Expensive Tools:
 ASIC design tools are very much expensive. You spend a huge amount.

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Evolution of PLD: FPGA
contains a set
of basic
functions
(gates, FFs,
memory cells)

Xilinx FPGA
Configuration
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 A field-programmable gate array (FPGA) is a logic
device that contains a two-dimensional array of
generic logic cells and programmable switches.

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Communication Engineering 27
 A field-programmable gate array (FPGA) is a logic
device that contains a two-dimensional array of
generic logic cells and programmable switches.
 A logic cell can be configured (i.e., programmed) to
perform a simple function
 A programmable switch can be customized to
provide interconnections among the logic cells
 A custom design can be implemented by specifying
the function of each logic cell and selectively setting
the connection of each programmable switch

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 Once the design and synthesis are completed, we can
use a simple adaptor cable to download the desired
logic cell and switch configuration to the FPGA
device
 Since this process can be done "in the field" rather

than "in a fabrication facility (fab)," the device is

known as field programmable.

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 A logic cell usually contains a small configurable combinational circuit with a D-type flip-flop
(DFF)
 The most common method to implement a configurable combinational circuit is a look-up table
(LUT). An n-input LUT can be considered as a small 2n-by-1 memory
 By properly writing the memory content, we can use a LUT to implement any n-input
combinational function

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Communication Engineering 30
 Logic cell
◦ The most basic element of the Spartan-3 device is a logic
cell (LC), which contains a four-input LUT and a DFF
 Slice
◦ In Xilinx terms, two logic cells are grouped to form a slice
 CLB
◦ Four slices are grouped to form a configurable logic block
(CLB)
 Macro Cell
◦ The Spartan-3 device contains four types of macro blocks:
combinational multiplier, block RAM, digital clock
manager (DCM), and input/output block (IOB)

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Communication Engineering 31
 Array Multiplier
◦ The combinational multiplier accepts two 18-bit numbers as
inputs and calculates the product
 Block RAM
◦ The block RAM is an 18K-bit synchronous SRAM that can
be arranged in various types of configurations
 DCM
◦ A DCM uses a digital-delayed loop to reduce clock skew
and to control the frequency and phase shift of a clock signal
 IOB
◦ An IOB controls the flow of data between the device's I/0
pins and the internal logic. It can be configured to support a
wide variety of I/0 signaling standards.

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 Module Declaration
A module is the principal design entity in Verilog. The first line of a module
declaration specifies the name and port list (arguments).

 The next few lines specifies the i/o type and width of each port. The default port
width is 1 bit.
Then the port variables must be declared wire, wand,. . ., reg The default is wire.

 Typically inputs are wire since their data is latched outside the module.

 Outputs are type reg if their signals were stored inside an always or initial block

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 Syntax
module module_name (port_list);
in1 my_module out1   input [msb:lsb] input_port_list;
in2 out2   output [msb:lsb] output_port_list;
  inout [msb:lsb] inout_port_list;
f          ... statements ...
endmodule
inN outM

module my_module(out1, .., inN);

output out1, .., outM;

Everything writen in Verilog must be input in1, .., inN;

inside a module
exception: compiler directives
.. // declarations
.. // description of f (maybe
.. // sequential)

endmodule
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Communication Engineering 34
 Note : All keywords are defined in lower case

Examples :
 module, endmodule
 input, output, inout
 reg, integer, real, time
 not, and, nand, or, nor, xor
 parameter
 begin, end
 fork, join
 specify, endspecify

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 Input, Output, Inout
These keywords declare input, output and bidirectional
ports of a module or task.
 Input and inout ports are of type wire.
 An output port can be configured to be of type wire, reg,
wand, wor or tri.
 The default is wire.

Syntax
 input [msb:lsb] input_port_list;
 output [msb:lsb] output_port_list;
 inout [msb:lsb] inout_port_list;

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 0: zero, logic low, false, ground

 1: one, logic high, power

 X: unknown

 Z: high impedance, unconnected, tri-state

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 &&  logical AND
 ||  logical OR
 ! logical NOT
 Operands evaluated to ONE bit value: 0, 1 or x
 Result is ONE bit value: 0, 1 or x

A = 1; A && B  1 && 0  0
B = 0; A || !B  1 || 1  1
C = x; C || B  x || 0  x

but
butC&&B=0
C&&B=0

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 &  bitwise AND
 |  bitwise OR
 ~  bitwise NOT
 ^  bitwise XOR
 ~^ or ^~  bitwise XNOR

 Operation on bit by bit basis

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 c = ~a; c = a & b;

 a = 4’b1010;
b = 4’b1100;

c = a ^ b;

 a = 4’b1010;
b = 2’b11;

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 >>  shift right
 <<  shift left
 a = 4’b1010;
d = a >> 2;// d = 0010,c = a << 1;// c =
0100
 cond_expr ? true_expr : false_expr

A
1
Y
B Y = (sel)? A : B;
0
sel

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Format : <size>’<base><value>
Example : 8’d16
8’h10
8’b00010000
8’o20

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 Value set and strengths
 Nets and Registers
 Vectors
 Integer, Real, and Time Register Data Types
 Arrays
 Memories
 Parameters
 Strings

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 Used to represent connections between HW elements
◦ Values continuously driven on nets
 Keyword: wire
◦ Default: One-bit values
 unless declared as vectors
◦ Default value: z
 For trireg, default is x
◦ Examples
 wire a;
 wire b, c;
 wire d=1’b0;

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 Registers represent data storage elements
◦ Retain value until next assignment
◦ NOTE: this is not a hardware register or flipflop
◦ Keyword: reg
◦ Default value: x
◦ Example:
reg reset;
initial
begin
reset = 1’b1;
#100 reset=1’b0;
end

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 Net and register data types can be declared as vectors
(multiple bit widths)
 Syntax:

◦ wire/reg [msb_index : lsb_index] data_id;

 Example
wire a;
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg clock;
reg [0:40] virtual_addr;

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 Consider
wire [7:0] bus;
wire [31:0] busA, busB, busC;
reg [0:40] virtual_addr;
 Access to bits or parts of a vector is possible:
busA[7]
bus[2:0] // three least-significant bits of bus
// bus[0:2] is illegal.
virtual_addr[0:1] /* two most-significant bits
* of virtual_addr
*/

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 Integer
◦ Keyword: integer
◦ Very similar to a vector of reg
 integer variables are signed numbers
 reg vectors are unsigned numbers
◦ Bit width: implementation-dependent (at least 32-bits)
 Designer can also specify a width:
integer [7:0] tmp;
◦ Examples:
integer counter;
initial
counter = -1;

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 Real
◦ Keyword: real
◦ Values:
 Default value: 0
 Decimal notation: 12.24
 Scientific notation: 3e6 (=3x106)
◦ Cannot have range declaration
◦ Example:
real delta;
initial
begin
delta=4e10;
delta=2.13;
end
integer i;
initial
i = delta; // i gets the value 2 (rounded value of 2.13)

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 Time
◦ Used to store values of simulation time
◦ Keyword: time
◦ Bit width: implementation-dependent (at least 64)
◦ $time system function gives current simulation time
◦ Example:
time save_sim_time;
initial
save_sim_time = $time;

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 Only one-dimensional arrays supported
 Allowed for reg, integer, time
◦ Not allowed for real data type
 Syntax:
<data_type> <var_name>[start_idx : end_idx];
 Examples:
integer count[0:7];
reg bool[31:0];
time chk_point[1:100];
reg [4:0] port_id[0:7];
integer matrix[4:0][4:0]; // illegal

count[5]
chk_point[100]
port_id[3]
 Note the difference between vectors and arrays

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 RAM, ROM, and register-files used many times in
digital systems
 Memory = array of registers in Verilog
 Word = an element of the array
◦ Can be one or more bits
 Examples:
reg membit[0:1023];
reg [7:0] membyte[0:1023];
membyte[511]
 Note the difference (as in arrays):
reg membit[0:127];
reg [0:127] register;

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 Similar to const in C
◦ But can be overridden for each module at compile-time
 Syntax:
parameter <const_id>=<value>;
 Gives flexibility
◦ Allows to customize the module
 Example:
parameter port_id=5;
parameter cache_line_width=256;
parameter bus_width=8;
wire [bus_width-1:0] bus;

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 Strings are stored in reg variables.
 8-bits required per character
 The string is stored from the least-significant part
to the most-significant part of the reg variable
 Example:
reg [8*18:1] string_value;
initial
string_value = “Hello World!”;
 Escaped characters
◦ \n: newline \t: tab
◦ %%: % \\: \
◦ \”: “ \ooo: character number in octal

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 Data Flow Description
 Behavioral Description
 Structural Description

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Communication Engineering 55