Microprocessor based Design

for Biomedical Applications

MBE 3 – MDBA

II : The ATmega8
Basic Features (1)
II: Atmega8 – Basic features

ATmega8 - RISC Architecture

● 130 Instructions – Most Single-clock Cycle Execution

● 32 x 8 General Purpose Working Registers
● 64 x 8 Special Function Registers (I/O Registers)
● Up to 16 MIPS Throughput at 16 MHz
● On-chip 2-cycle Multiplier

Nonvolatile Program and Data Memories

● 8K Bytes of In-System Self-Programmable Flash

10,000 Write/Erase Cycles
● Optional Boot Code Section with Independent Lock Bits
● 512 Bytes EEPROM (100,000 Write/Erase Cycles)
● 1K Byte Internal SRAM
● Programming Lock for Software Security
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Peripheral Features

● Two 8-bit Timer/Counters

● One 16-bit Timer/Counter with Capture Mode
● Real Time Counter with Separate Oscillator
● Three PWM Channels
● 6-channel ADC with 10 resp 8 Bit resolution (TQFP: 8 channels)
● Two-wire Serial Interface (TWI)
● Programmable Serial USART
● Master/Slave SPI Serial Interface
● Programmable Watchdog Timer with On-chip Oscillator
● On-chip Analog Comparator
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Special Microcontroller Features

● Programmable Brown-out Detection

● Internal Calibrated RC Oscillator
● External and Internal Interrupt Sources
● Five Sleep Modes

I/O and Packages

● 23 Programmable I/O Lines

● 28-lead PDIP, 32-lead TQFP, and 32-pad MLF
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Operating Voltages

● 2.7 - 5.5V (ATmega8L)

● 4.5 - 5.5V (ATmega8)

Speed Grades

● 0 - 8 MHz (ATmega8L)
● 0 - 16 MHz (ATmega8)

Power Consumption at 4 Mhz, 3V, 25°C

● Active: 3.6 mA
● Idle Mode: 1.0 mA
● Power-down Mode: 0.5 μA
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ATmega8 Pinout and Packages (DIP and TQFP)

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Mega8 CPU Core

● Seperate Instruction and

Data Memories (Harvard)

● all 32 General Purpose

Registers connected to
ALU

● I/O Modules connected to

Data Bus and accessible via
Special Function Registers

ATmega8 Core Architecture

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II: Atmega8 – Basic features

Harvard architecture

● Separate storage and signal pathways for

instructions and data.

● History: Harvard Mark I

relay-based computer

● word width, timing, and implementation

technology of instruction and data memories
can differ.

● Contrast: ‘Von Neumann’ - architecture:

Instructions and data use the same signal
pathways and memory.
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Harvard architecture

● Ability to fetch the next instruction at the

same time it completes the current
instruction.

● Speed is gained at the expense of more

complex electrical circuitry.

In a computer with Harvard architecture, the CPU can read

an instruction and data from memory at the same time.
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Pin and Port Overview:

GND: Ground (0V)

VCC: Digital Supply Voltage (2,7 – 5,5V)
AVCC: Analog Supply Voltage
connect to low-pass filtered VCC
AREF: Analog Reference Voltage, usually AVCC
/Reset: Low level on this pin will generate a reset

Port B, Port C, Port D:

General Purpose 8 Bit bidirectional I/O - Ports,
optional internal pullup-resistors when configured as input
output source capability: 20mA

Special Functions of the Ports available as configured using the SFRs:

Port D: Uart, external Interrupts, Analog Comparator

Port B: External Oscillator/Crystal, SPI
Port C: A/D converters, TWI
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Memory organization
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AVR Memory organization:

● Program Flash Memory:

On-chip, in system programmable

8 Kbytes, organized in 4K 16 bit words

Program Counter (PC) = 12 bits

Accessible via special instructions: LPM, SPM

Boot Loader support: Boot Flash Section,

SPM can be executed only from Boot Flash
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AVR Memory organization:

● EEPROM - Memory:

512 Bytes, single Bytes can be read and written

Special EEPROM read and write procedure using SFRs:

EEPROM Address Register, EEPROM Data Register,

EEPROM Control Register
C – Library Functions available

Precautions to prevent EEPROM memory corruption:

● no flash memory or interrupt operations

● stable power supply
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AVR Memory organization:

● SRAM Data Memory:

32 GPR’s and
64 SFR’s mapped
to SRAM memory space

SFR’s accessed
via in / out instructions
(I/O-registers)

1 Kbytes of internal
SRAM can be accessed
from address 0x060
to address 0x45f

5 Direct and indirect addressing modes

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AVR Memory organization:

● General Purpose Registers:

Although not being physically

implemented as SRAM locations,
GPR’s can be accessed
by SRAM locations

X, Y and Z 16-bit registers

can be used for indirect addressing

ALU - Input / output schemes:

one 8-bit operand, 8-bit result
two 8-bit operands, 8-bit result
two 8-bit operands, 16-bit result
one 16-bit operand, 16-bit result
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I/O Memory (SFR) Overview

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I/O Memory (SFR) Overview

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Important I/O Registers:

SREG – Status Register

Bit 7 – I: Global Interrupt Enable

Bit 6 – T: Bit Copy Storage
Bit 5 – H: Half Carry Flag
Bit 4 – S: Sign Bit
Bit 3 – V: Two’s Complement Overflow Flag
Bit 2 – N: Negative Flag
Bit 1 – Z: Zero Flag
Bit 0 – C: Carry Flag
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Important I/O Registers:

Stack Pointer (SPH and SPL)

● Stack is a LIFO buffer located in SRAM

● Stack Pointer addresses the current location
● Push and pop instructions write / read from Stack
● Enter or return from subroutines / interrupt routines:
Address and Parameters transferred via Stack
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Clock Options
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System Clock Options:

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System Clock Options:

● Clock Muliplexer selects the clock

source according to FUSE settings

● Clock Control Unit distributes clocks

clocks can be halted to reduce power
consumption

● CPU Clock: CPU, ALU, GPRs

● I/O Clock: Ports, Timers, SPI, UART

● ADC Clock: seperate cock for ADC

noise reduction in sleep mode

● Asynchronous Timer Clock:

external 32kHz Crystal for realtime clock,
keeps timer module running during sleep mode
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System Clock Options - FUSE bits:

● The four CKSEL Bits of the FUSE – Byte select the main Clock Source

● The startup time to stabilize power supply and oscillator can be changed

with the SUT fuses

● The device is shipped with CKSEL = 0001 ( 1 MHZ internal RC oscillator )

and SUT = 10 ( slowly rising power, 65ms )
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System Clock Options - using an external crystal:

● CKOPT influences the output swing of the inverting oscillator amplifier

(1 = full rail to rail swing, 0 = power save mode)

● For crystals from 3 – 8 MHz set CKOPT = 1 and CKSEL3..1 = 111

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System Clock Options - using the internal RC oscillator

● Fixed 1, 2, 4 or 8 MHz clock

● works without external components

● changes with temperature and operating voltage

detailed information on other clock options, startup times, calibration

is found in the ATmega8 data sheet, pp. 23
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I/O Ports
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I/O Ports

● General Purpose IO : Data Direction Input or Output

● Internal Pullup can be used for Input Pins
● Output driver can source 20mA current
● protection diodes to GND and VCC
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I/O Ports

● 3 I/O-Registers for each port:

Data Register (r/w):

PORTB, PORTC, PORTD

Data Direction Register (r/w):

DDRB, DDRC, DDRD

Port Input Pin Register (r):

PINB, PINC, PIND

The Bits of these registers set the configuration for one Port Pin.
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I/O Ports
General Digital IO

Logic of GPIO-Ports:

DDx
PORTx
PINx

Common to all Ports:

Pullup disable (PUD),
SLEEP
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I/O Ports – Configuration and usage

C-Example 1 - Configure Pin B3 as output, set output level to VCC:

DDRB |= (1<<3); PORTB |= (1<<3);

C-Example 2 - Configure Pin D2 as input with pullup, read pin value:

DDRD &= ~(1<<2); PORTD |= (1<<2); uint8_t x = PIND & (1<<2);

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Alternate Port functions Port B

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Alternate Port functions Port C

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Alternate Port functions Port D

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Reset- and Interrupt Handling

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Interrupt Processing

● several Interrupt Sources:

External Interrupts, Timer, Bus-Peripherals,
ADC, EEPROM

● individual Interrupt-Enable bits in the SFR‘s

● global interrupt enable Bit in SREG,

set with sei() and clear with cli() instruction

● flagged (remembered) and non-flagged interrupt sources

● lowest addresses in program memory reserved

for the interrupt vector table

● higher priority interrupts have lower addresses

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Reset-Vector and
Interrupt-Vectors

● Word addresses
0, 1 – 19 in Flash Ram

● When a reset or
interrupt occurs,
the CPU calls
the address

● Install an Interrupt
Handler: modify
the vector table to
jump to your user-
handler

● return from interrupt:

reti
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Reset-Vector and
Interrupt-Vectors

● example shows
full featured
vector table

● 19 handlers installed

● program execution
after reset:
jmp RESET ($013)

● Main program is
located at $013,
beyond the vectors
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Reset- and Interrupt- Vectors

● Reset vector can be set to the Bootloader section using the

BOOTRST fuse bit

● Interrupt vectors can be set to the Bootloader

section using the IVSEL bit of the General Interrupt Contol Register
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AVR Reset Sources:

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Reset Sources:

• Power-on Reset: supply voltage is

below the Power-on Reset threshold

• External Reset: low level is present on

/RESET – input pin

• Watchdog Reset: Watchdog Timer

enabled and period expires

• Brown-out Reset: Brown-out Detector

enabled and supply voltage below
threshold

MCUCSR provides information on which reset source caused a CPU reset

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Reset Voltage Thresholds

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Reset Voltage Thresholds:

Example:
Power-on Reset

Example:
Brown Out Reset
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External Interrupts Int0 and Int1:

• Int0 connected to PD2

• Int1 connected to PD3
• asynchronous operation: can wake up CPU
• rising/falling edge or low level can trigger interrupt,
defined by Interrupt Sense control – bits of MCUCR SFU
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External Interrupts Int0 and Int1:

• Int0 and Int1 have to be enabled by the GICR (+ I-bit in SREG)

• flagged interrupts: General Interrupt Flag Register (GIFR)

indicates when an interrupt request happened

• flags are cleared by executing the interrupt service routine (ISR)

or by writing 1 to the flag bit of GIFR
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8-bit Timer / Counter0

• 10-bit clock Prescaler

timer-clk (t0) = clk (IO) / prescaler

• External clock source T0 connected to PD4

cannot be prescaled, clk(ext) <= clk (IO) / 2.5
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8-bit Timer / Counter0 - prescaler operation

No prescaler

MAX=0xff
BOTTOM=0

Prescaler = 8
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8-bit Timer / Counter0 usage

Timer/Counter0 Control Register (TCCR0), Bits CS02-CS00

select Clock Source and Prescaler Value :
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8-bit Timer / Counter0 usage

Timer/Counter0 Register (TCNT0) :

read/write, incremented per CLK cycle, overflow: 0xff

• A Reload-Value is used to fine-tune the interrupt interval

• write Reload-Value to TCNT0 in the ISR

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8-bit Timer / Counter0 usage

Timer/Counter Interrupt Mask Register (TIMSK) :

Bit 0 : Timer 0 interrupt enable
set 1 to enable timer 0 overflow interrupt ( + I-Bit in SREG)

Timer Interrupt Flag Register (TIFR) :

TOV0 indicates a Timer0 overflow, cleared by hardware when
the ISR is executed or by writing 1 to the flag