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Transistor Sizing

The document discusses transistor sizing for an inverter. To minimize area, the channel length is set to the minimum allowed and the width to length ratio (W/L)n is typically between 1 to 1.5. Commonly, the ratio (W/L)p is set to twice (W/L)n to optimize noise margins and transition times while minimizing area and capacitance. The width to length ratios can then be increased to further reduce transition times, though this increases area and the inverter's equivalent capacitance C, which is the sum of its intrinsic Cint and extrinsic Cext components.

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52 views14 pages

Transistor Sizing

The document discusses transistor sizing for an inverter. To minimize area, the channel length is set to the minimum allowed and the width to length ratio (W/L)n is typically between 1 to 1.5. Commonly, the ratio (W/L)p is set to twice (W/L)n to optimize noise margins and transition times while minimizing area and capacitance. The width to length ratios can then be increased to further reduce transition times, though this increases area and the inverter's equivalent capacitance C, which is the sum of its intrinsic Cint and extrinsic Cext components.

Uploaded by

ShwetaGautam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Transistor Sizing

Inverter
The selection of appropriate values for the channel length L and the (W/L) ratios for the
two transistors QN and QP in an inverter.

1. To minimize area, the length of all channel is usually made equal to the minimum
length permitted by the given technology.

2. To minimize area, (W/L)n range 1 to 1.5. (W/L)p relative to (W/L)n has influence
on the noise margins and tPLH . Both are optimized by matching QP and QN but
wasteful of area and, and can increase the effective capacitance C, so that although tPLH
is made equal to tPHL.
Thus, selecting (W/L)p = (W/L)n is a possibility, and (W/L)p = 2(W/L)n is a frequently used.

3. Having settled on an appropriate ratio of (W/L)p to (W/L)n, we still have to select


(W/L)n to reduce tP and thus allow higher speeds of operation. Any increase in (W/L)n
and proportionally in (W/L)p will of course increase area, and hence the inverter
contribution to the value of the equivalent capacitance C. To be more precise we
express C as the sum of an intrinsic component Cint contributed by QN and QP of
the inverter, and an extrinsic component Cext resulting from the wiring and the input
capacitance of the driven gates,

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