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8085 Architecture

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 8085
• 8-bit general purpose microprocessor 
• Capable to address 64k of memory
• Forty pins, requires +5 V single power supply
• 3-MHz single-phase clock.

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Block Diagram

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 Pin Diagram of 8085
+5v power
This signal
supply.
Frequency is internally divided write control
can be
by two operate system at 3- read control
signal (active
used as the
MHz, the crystal should have a signal
low). (active
system
frequency of 6-MHz. low).
Written into
clock for
memory
other read
selected
AD7 – AD0 the data
memory.
memory
devices.
A15 - A8 
bi-directional
dual purpose uni
used as a directional
low order and used as
address bus  a high order
address bus.
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 Timing Diagram
Instruction Cycle:

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Machine Cycle:

time required to access the memory or

input/output devices is called machine cycle

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T- States:
The machine cycle and instruction cycle takes
multiple clock periods.
periods

A portion of an operation carried out in one

system clock period is called as T-state

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• Microprocessor operates with reference to
clock signals.
signals
• X1 and X2 we provide clock signals and this
frequency is divided by two.
• This frequency is called as the operating
frequency.
frequency

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 Interrupts
• An interrupt is considered to be an emergency
signal that may be serviced.
– The Microprocessor may respond to it as soon as
possible.
• What happens when MP is interrupted ?
– When the Microprocessor receives an interrupt signal,
it suspends the currently executing program and
jumps to an Interrupt Service Routine (ISR) to respond
to the incoming interrupt.
– Each interrupt will most probably have its own ISR.

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 Interrupts in 8085 INTA

Interrupt

Save Send out

program Disable interupt
counter interrupts acknowledge

Main routine
Go to
service
Go back
routine

Get EI
original RET
program
counter Service routine

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• Classification of Interrupts
Interrupts can be classified into two types:

• Maskable Interrupts (Can be delayed or Rejected)

• Enable Or Disable By EI And DI Instruction

• Non-Maskable Interrupts (Can not be delayed or Rejected)

Interrupts can also be classified into two types:

• Vectored (the address of the service routine is hard-wired)

• Non-vectored (the address of the service routine needs to

be supplied externally by the device)
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 Responding to Interrupts
Responding  “delayed or immediate”
immediate
“ Maskable or Non-maskable ”
Redirecting the execution to the ISR
“ Pre Defined Address or Address to be Defined”
Defined
“ Vectored or Non-vectored ”
◦ Vectored: The address of the subroutine is already
known to the Microprocessor

◦ Non Vectored: The device will have to supply the

address of the subroutine to the Microprocessor

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 5 - Interrupts in 8085

• There are 5 interrupt inputs:

– TRAP (non maskable)
– RST7.5
– RST6.5
– RST5.5
– INTR

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 The 8085 Interrupts
• The 8085 has 5 interrupt inputs.
– The INTR input.
• The INTR input is the only non-vectored interrupt.
• INTR is maskable using the EI/DI instruction pair.

– RST 5.5, RST 6.5, RST 7.5 are all automatically

vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.

– TRAP is the only non-maskable interrupt in the 8085

• TRAP is also automatically vectored

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 The 8085 Interrupts

VECTOR
Interrupt name Maskable Vectored
ADDRESS

TRAP No Yes 0024H

RST 7.5 Yes Yes 003CH

RST 6.5 Yes Yes 0034H

RST 5.5 Yes Yes 002CH

INTR Yes No --
 8085 INTERRUPTS
• The ‘EI’
EI instruction is a one byte instruction
and is used to Enable the maskable
interrupts.

• The ‘DI’
DI instruction is a one byte instruction
and is used to Disable the maskable
interrupts.

• The 8085 has a single Non-Maskable

interrupt. “TRAP”
8085 Interrupts

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Interrupt Vectors and the Vector Table
• An interrupt vector is a pointer the memory
 location of an interrupt handler, which
prioritizes interrupts and saves them in a queue
• All interrupts (vectored or otherwise) are
mapped onto a memory area called the
Interrupt Vector Table (IVT).
– The IVT is usually located in memory page 00
(0000H - 00FFH).
– The purpose of the IVT is to hold the vectors that
redirect the microprocessor to the right place when
an interrupt arrives.

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The 8085 Non-Vectored Interrupt
Process
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every
instruction.
3. If INTR is high, MP completes current instruction, disables the
interrupt and sends INTA (Interrupt acknowledge) signal to the
device that interrupted
4. INTA allows the I/O device to send a RST instruction through data
bus.
5. Upon receiving the INTA signal, MP saves the memory
location of the next instruction on the stack and the
program is transferred to ‘call’ location (ISR Call) specified
by the RST instruction

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 The 8085 Non-Vectored
Interrupt Process

6. Microprocessor Performs the ISR.

7. ISR must include the ‘EI’ instruction to enable the further
interrupt within the program.
8. RET instruction at the end of the ISR allows the MP to
retrieve the return address from the stack and the program
is transferred back to where the program was interrupted.

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 The 8085 Maskable/Vectored
Interrupts
• The 8085 has 3 Masked/Vectored interrupt inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the following
table:
Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors for the
RST instructions. That’s why they have names like RST 5.5 (RST
5 and a half).

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 Masking RST 5.5, RST 6.5 and
RST 7.5
• These three interrupts are masked
at two levels:
• Through the Interrupt Enable flip flop
and the EI/DI instructions.
• The Interrupt Enable flip flop controls
the whole maskable interrupt process.
process
• Through individual mask flip flops that
control the availability of the individual
interrupts. These flip flops control the
interrupts individually.
individually

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Maskable Interrupts and vector locations
RST7.5 Memory
RST 7.5

M 7.5

RST 6.5

M 6.5

RST 5.5

M 5.5

INTR

Interrupt
Enable
Flip Flop

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 The 8085 Maskable/Vectored Interrupt
Process
1. The interrupt process should be enabled using the EI
instruction.
2. The 8085 checks for an interrupt during the execution of
every instruction.
3. If there is an interrupt, and if the interrupt is enabled
using the interrupt mask,
mask the microprocessor will
complete the executing instruction,
instruction and reset the
interrupt flip flop.
flop
4. The microprocessor then executes a call instruction that
sends the execution to the appropriate location in the
interrupt vector table.

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 The 8085 Maskable/Vectored Interrupt
Process

5. When the microprocessor executes the call instruction, it

saves the address of the next instruction on the stack.
6. The microprocessor jumps to the specific service routine.
7. The service routine must include the instruction EI to re-
enable the interrupt process.
8. At the end of the service routine, the RET instruction
returns the execution to where the program was
interrupted.

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 Manipulating the Masks
• The Interrupt Enable flip flop is manipulated
using the EI/DI instructions.

• The individual masks for RST 5.5, RST 6.5

and RST 7.5 are manipulated using the SIM
instruction.
– This instruction takes the bit pattern in the
Accumulator and applies it to the interrupt mask
enabling and disabling the specific interrupts.

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 How SIM Interprets the Accumulator
7 6 5 4 3 2 1 0

M6.5
SDO

M5.5
M7.5
SDE

MSE
R7.5
XXX
Serial Data Out RST5.5 Mask

RST7.5 }
RST6.5 Mask 0 - Available
1 - Masked

Mask
Mask Set Enable
Enable Serial Data
0 - Ignore bits 0-2
0 - Ignore bit 7
1 - Set the masks according
1 - Send bit 7 to SOD pin
to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

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 SIM and the Interrupt Mask
• Bit 0 is the mask for RST 5.5
• Bit 1 is the mask for RST 6.5
• Bit 2 is the mask for RST 7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.

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• Bit 3 (Mask Set Enable - MSE) is an enable
for setting the mask.
• If it is set to 0 the mask is ignored and the old
settings remain.
• If it is set to 1, the new setting are applied.
• The SIM instruction is used for multiple
purposes and not only for setting interrupt
masks.
– It is also used to control functionality such as Serial
Data Transmission.
– Therefore, bit 3 is necessary to tell the
microprocessor whether or not the interrupt masks
should be modified

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 SIM and the Interrupt Mask
• The RST 7.5 interrupt is the only 8085 interrupt that has memory.
– If a signal on RST7.5 arrives while it is masked, a flip flop will
remember the signal.
– When RST7.5 is unmasked, the microprocessor will be interrupted
even if the device has removed the interrupt signal.
– This flip flop will be automatically reset when the microprocessor
responds to an RST 7.5 interrupt.

• Bit 4 of the accumulator in the SIM instruction allows explicitly

resetting the RST 7.5 memory even if the microprocessor did not
respond to it.
• Bit 5 is not used by the SIM instruction

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 Using the SIM Instruction to Modify the Interrupt
Masks

• Example: Set the interrupt masks so that

RST5.5 is enabled, RST6.5 is masked, and
RST7.5 is enabled.
– First, determine the contents ofthe accumulator

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Using the SIM Instruction to Modify the Interrupt
Masks

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 Triggering Levels

• RST 7.5 is positive edge sensitive.

• When a positive edge appears on the RST7.5 line, a logic 1 is
stored in the flip-flop as a “pending” interrupt.
• Since the value has been stored in the flip flop, the line does
not have to be high when the microprocessor checks for the
interrupt to be recognized.
• The line must go to zero and back to one before a new
interrupt is recognized.

• RST 6.5 and RST 5.5 are level sensitive.

• The interrupting signal must remain present until the
microprocessor checks for interrupts.

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 Determining the Current
Mask Settings
• RIM instruction: Read Interrupt Mask
– Load the accumulator with an 8-bit pattern
showing the status of each interrupt pin and mask.

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RIM sets the Accumulator’s different bits

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 The RIM Instruction and the
Masks
• Bits 0-2 show the current setting of the mask for
each of RST 7.5, RST 6.5 and RST 5.5
• They return the contents of the three mask flip flops.
• They can be used by a program to read the mask settings in
order to modify only the right mask.

• Bit 3 shows whether the maskable interrupt

process is enabled or not.
• It returns the contents of the Interrupt Enable Flip Flop.
• It can be used by a program to determine whether or not
interrupts are enabled.

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 The RIM Instruction and the
Masks
• Bits 4-6 show whether or not there are pending
interrupts on RST 7.5, RST 6.5, and RST 5.5
• Bits 4 and 5 return the current value of the RST5.5 and
RST6.5 pins.
• Bit 6 returns the current value of the RST7.5 memory
flip flop.

• Bit 7 is used for Serial Data Input.

• The RIM instruction reads the value of the SID pin on
the microprocessor and returns it in this bit.

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 Pending Interrupts
• Since the 8085 has five interrupt lines,
interrupts may occur during an ISR and remain
pending.
– Using the RIM instruction, it is possible to can
read the status of the interrupt lines and find if
there are any pending interrupts.

– See the example of the class

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 TRAP
• TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot be
disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again
until it goes low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.
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 Issues in Implementing INTR
Interrupts
• How long must INTR remain high?
– The microprocessor checks the INTR line one clock cycle before the
last T-state of each instruction.
– The INTR must remain active long enough to allow for the longest
instruction.
– The longest instruction for the 8085 is the conditional CALL
instruction which requires 18 T-states.
• Therefore, the INTR must remain active for 17.5 T-states.
• If f= 3MHZ then T=1/f and so, INTR must remain active for
[ (1/3MHZ) * 17.5 ≈ 5.8 micro seconds].

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 Issues in Implementing INTR
Interrupts
• How long can the INTR remain high?
– The INTR line must be deactivated before the EI is
executed. Otherwise, the microprocessor will be
interrupted again.
– Once the microprocessor starts to respond to an
INTR interrupt, INTA becomes active (=0).

Therefore, INTR should be turned off as soon as

the INTA signal is received.
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The 8085 Interrupts
PIN 7
RST 7.5

M7.5’
R 7.5

RST 7.5
ACKNOWLEDGE
MENT

MSE
 Addressing Modes of 8085
• To perform any operation, we have to give the
corresponding instructions to the
microprocessor.
• In each instruction, programmer has to specify
3 things:
– Operation to be performed.
– Address of source of data.
– Address of destination of result.

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Addressing Modes of 8085
The method by which the address of source of
data or the address of destination of result is
given in the instruction is called Addressing
Modes.
The term addressing mode refers to the way
in which the operand of the instruction is
specified.

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Types of Addressing Modes
• Intel 8085 uses the following addressing
modes:
1. Direct Addressing Mode
2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode

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 Direct Addressing Mode
In this mode, the address of the operand is
given in the instruction itself.

LDA 2500 H Load the contents of memory location

2500 H in accumulator.
LDA is the operation.
2500 H is the address of source.
Accumulator is the destination.

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 Register Addressing Mode
• In this mode, the operand is in general purpose
register.
MOV A, B Move the contents of register B to A.

• MOV is the operation.

• B is the source of data.
• A is the destination.

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 Register Indirect Addressing
Mode
• In this mode, the address of operand is specified
by a register pair.
MOV A, Move data from memory location
M specified by H-L pair to accumulator.

• MOV is the operation.

• M is the memory location specified by H-L
register pair.
• A is the destination.
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 Immediate Addressing Mode
• In this mode, the operand is specified within
the instruction itself.
MVI A, 05 H Move 05 H in accumulator.

• MVI is the operation.

• 05 H is the immediate data (source).
• A is the destination.

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 Implicit Addressing Mode
If address of source of data as well as address of
destination of result is fixed, then there is no need
to give any operand along with the instruction.

CMA Complement accumulator.

CMA is the operation.

A is the source.
A is the destination.
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