The document discusses the ARM architecture used in many embedded systems. It describes how ARM processors use the RISC design philosophy with simple instructions that execute in single cycles. The ARM instruction set differs slightly from pure RISC with features like variable cycle instructions and conditional execution. Typical ARM-based embedded systems include peripherals connected via buses like the Advanced Microcontroller Bus Architecture (AMBA) to an ARM processor controlling memory and carrying out tasks scheduled by initialization code and an operating system.
The document discusses the ARM architecture used in many embedded systems. It describes how ARM processors use the RISC design philosophy with simple instructions that execute in single cycles. The ARM instruction set differs slightly from pure RISC with features like variable cycle instructions and conditional execution. Typical ARM-based embedded systems include peripherals connected via buses like the Advanced Microcontroller Bus Architecture (AMBA) to an ARM processor controlling memory and carrying out tasks scheduled by initialization code and an operating system.
The document discusses the ARM architecture used in many embedded systems. It describes how ARM processors use the RISC design philosophy with simple instructions that execute in single cycles. The ARM instruction set differs slightly from pure RISC with features like variable cycle instructions and conditional execution. Typical ARM-based embedded systems include peripherals connected via buses like the Advanced Microcontroller Bus Architecture (AMBA) to an ARM processor controlling memory and carrying out tasks scheduled by initialization code and an operating system.
The document discusses the ARM architecture used in many embedded systems. It describes how ARM processors use the RISC design philosophy with simple instructions that execute in single cycles. The ARM instruction set differs slightly from pure RISC with features like variable cycle instructions and conditional execution. Typical ARM-based embedded systems include peripherals connected via buses like the Advanced Microcontroller Bus Architecture (AMBA) to an ARM processor controlling memory and carrying out tasks scheduled by initialization code and an operating system.
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Embedded Systems-II
ARM architecture
DR. BIPIN CH. MANDI
ASST. PROFESSOR
IIIT NAYA RAIPUR
03/31/2020 IIIT NAYA RAIPUR 1
ARM processor The ARM processor -key component of many successful 32-bit embedded systems ARM cores-mobile phones, handheld organizers, and a multitude of other everyday portable consumer devices RISC (reduced instruction set computer) design philosophy was adapted by ARM Aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock speed RISC philosophy concentrates on reducing the complexity of instructions performed by the hardware
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RISC philosophy • RISC philosophy is implemented with four major design rules 1. Instructions—RISC processors have a reduced number of instruction classes. These classes provide simple operations that can each execute in a single cycle. 2. Pipelines—The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. 3. Registers—RISC machines have a large general-purpose register set. Any register can contain either data or an address. 4. Load-store architecture—The processor operates on data held in registers. Separate load and store instructions transfer data between the register bank and external memory.
RISC processor to be simpler, and thus
the core can operate at higher clock frequencies. CISC processors are more complex and operate at lower clock frequencies.
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ARM Design Philosophy A number of physical features by ARM processor design. 1. First, portable embedded systems require some form of battery power. The ARM processor has been specifically designed to be small to reduce power consumption and extend battery operation 2. High code density is another major requirement as limited memory due to cost and/or physical size restrictions 3. Embedded systems are price sensitive and use slow and low-cost memory devices. For high-volume applications like digital cameras, every cent has to be accounted for in the design 4. To reduce the area of the die taken up by the embedded processor 5. ARM has incorporated hardware debug technology within the processor
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Instruction Set for Embedded Systems The ARM instruction set differs from the pure RISC in several ways 1. Variable cycle execution for certain instructions—Not every ARM instruction executes in a single cycle. For example, load-store-multiple instructions 2. Inline barrel shifter leading to more complex instructions—The inline barrel shifter is a hardware component that preprocesses one of the input registers before it is used by an instruction. 3. Thumb 16-bit instruction set—ARM enhanced the processor core by adding a second 16-bit instruction set called Thumb that permits the ARM core to execute either 16- or 32-bit instructions 4. Conditional execution—An instruction is only executed when a specific condition has been satisfied 5. Enhanced instructions—The enhanced digital signal processor (DSP) instructions were added to the standard ARM instruction set to support fast 16×16-bit multiplier operations and saturation.
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ARM-based embedded system
An example of an ARM-based embedded device, a microcontroller.
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A typical embedded device based on an ARM core The ARM processor controls the embedded device. Different versions of the ARM processor are available to suit the desired operating characteristics.
Controllers coordinate important functional blocks of the system. Two
commonly found controllers are interrupt and memory controllers.
The peripherals provide all the input-output capability external to the
chip and are responsible for the uniqueness of the embedded device.
A bus is used to communicate between different parts of the device.
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ARM Bus Technology
The most common PC bus technology, the Peripheral Component Interconnect
(PCI) bus, connects such devices as video cards and hard disk controllers to the x86 processor bus.
There are two different classes 1. bus master—initiating a data transfer with another device across the same bus. 2. bus slaves—only of responding to a transfer request from a bus master device.
A bus has two architecture levels. 1. physical level that covers the electrical characteristics and bus width (16, 32, or 64 bits). 2. The second level deals with protocol—the logical rules that govern the communication between the processor and a peripheral.
ARM routinely specifies the bus protocol.
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AMBA Bus Protocol
The Advanced Microcontroller Bus Architecture (AMBA) was
introduced in 1996 and has been widely adopted as the on-chip bus architecture used for ARM processors. The first AMBA buses introduced were the ARM System Bus (ASB) and the ARM Peripheral Bus (APB). Using AMBA, peripheral designers can reuse the same design on multiple projects. Because there are a large number of peripherals developed with an AMBA interface, hardware designers have a wide choice of tested and proven peripherals for use in a device.
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Memory to have some form of memory to store and execute code to compare price, performance, and power consumption when deciding upon specific memory characteristics, such as hierarchy, width, and type hierarchy -the memory trade-offs: the fastest memory cache is physically located nearer the ARM processor core and the slowest secondary memory is set further away. width - the number of bits the memory returns on each access— typically 8, 16, 32, or 64 bits. The memory width has a direct effect on the overall performance and cost ratio. type-some of the more popular memory devices found in ARM-based embedded systems.
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Peripherals Controllers are specialized peripherals that implement higher levels of functionality. Two important types-memory and interrupt controllers 1. Memory controllers connect different types of memory to the processor bus. On power-up a memory controller is configured in hardware to allow certain memory devices to be active. 2. An interrupt controller provides a programmable governing policy that allows software to determine which peripheral or device can interrupt the processor at any specific time by setting the appropriate bits in the interrupt controller registers. There are two types -the standard interrupt and the vector interrupt controller (VIC). 1. The standard interrupt controller sends an interrupt signal to the processor core when an external device requests servicing by reading a device bitmap register in the interrupt controller. 2. The VIC is more powerful than the standard interrupt controller because it prioritizes interrupts and simplifies the determination of which device caused the interrupt
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Embedded System Software The operating system provides an infrastructure to control applications and manage hardware system resources. Many embedded systems do not require a full operating system but merely a simple task scheduler that is either event or poll driven.
Initialization (Boot) Code-Initialization code (or boot code) takes the
processor from the reset state to a state Operating System-The initialization process prepares Applications-The operating system schedules applications—code dedicated to handling a particular task
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Initialization (Boot) Code Initialization (Boot) Code - It usually configures the memory controller and processor caches and initializes some devices.
The initialization code handles a number of administrative tasks prior to
handing control over to an operating system image. Different tasks into three phases: initial hardware configuration, diagnostics, and booting. 1. Initial hardware configuration involves setting up the target platform so it can boot an image. 2. Diagnostics code tests the system by exercising the hardware target to check if the target is in working order 3. Booting involves loading an image and handing control over to that image. It is complicated if the system must boot different operating systems or different versions of the same operating system.
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Operating System An operating system organizes the system resources: the peripherals, memory, and processing time. ARM processors support over 50 operating systems. Two main categories: real-time operating systems (RTOSs) and platform operating systems. RTOSs provide guaranteed response times to events. Different operating systems have different amounts of control over the system response time. Two RTOSs A hard RTOS requires a guaranteed response to work at all. In contrast, a soft RTOS requires a good response time, but the performance degrades more gracefully if the response time overruns. Systems running an RTOS generally do not have secondary storage. Platform operating systems require a memory management unit to manage large, non real-time applications and tend to have secondary storage. The Linux is a typical example of a platform operating system. 03/31/2020 IIIT NAYA RAIPUR 14 Applications The operating system schedules applications—code dedicated to handling a particular task.
ARM processor is found in networking applications like home gateways,
DSL modems for high-speed Internet communication, and 802.11 wireless communication
ARM processors are also found in mass storage devices (hard drives) and imaging products (inkjet printers)—that are cost sensitive and high volume.
ARM processors are not found in leading-edge high performance
because these applications tend to be low volume and high cost
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Summary
ARM-modified RISC targets good code density and low power consumption. An embedded system consists of a processor core surrounded by caches, memory, and peripherals. The system is controlled by operating system software that manages application tasks. RISC design philosophy-to improve performance by reducing the complexity of instructions, to speed up instruction, to provide a large register, and to use a load-store architecture.
The ARM design philosophy also incorporates some non-RISC ideas:
■ Variable cycle execution on certain instructions to save power, area, and code size. ■ It adds a barrel shifter to expand the capability of certain instructions. ■ It uses the Thumb 16-bit instruction set to improve code density.
