Data Flow-Level

Modeling

© 2006 Xilinx, Inc. All Rights Reserved

 Objectives
After completing this module, you will be able to:
• Combine operators and operands within expressions
• Use assign statement to model combinatorial logic
• Specify when to use wire (net) data types
• Specify delay and timing parameters

Data Flow-Level Modeling - 10 - 2 © 2006 Xilinx, Inc. All Rights Reserved

 Outline
• Continuous Assignment
• Delay Specification
• Summary
• Appendix: Gate-Level
Modeling

Data Flow-Level Modeling - 10 - 3 © 2006 Xilinx, Inc. All Rights Reserved

 Levels of Abstraction

Behavioral f

RTL

AND_
OR
Data Flow
and Gate

Switch

Data Flow-Level Modeling - 10 - 4 © 2006 Xilinx, Inc. All Rights Reserved

 Continuous Assignments
• Continuous assignments are the basic construct for data flow-level
modeling
– The expression can use any of the Verilog operators described earlier
module LOGIC_1 (port listing…) ;
...
wire OUT1, A,B ; Operator
...
assign OUT1 = A & B ; Operands
... net or reg

Must be net, Signal or

not reg ! bus

Data Flow-Level Modeling - 10 - 5 © 2006 Xilinx, Inc. All Rights Reserved

 Continuous Assignments
• The continuous assignment is re-evaluated whenever any of the
operands (inputs) change value
assign Out1 = ((A & Sel[0] & Sel[1]) |
A (B & ~Sel[0] & Sel[1]) |
Sel[1] (C & Sel[0] & ~Sel[1]) |
Sel[0]
(D & ~Sel[0] & ~Sel[1])) ;
B
Sel[1]
Sel[0] Out1
C
Sel[1]
Sel[0]
D
Sel[1] This code models a 4:1 multiplexer
Sel[0]

Data Flow-Level Modeling - 10 - 6 © 2006 Xilinx, Inc. All Rights Reserved

 Implicit Assignment
Statements
• An implicit, continuous assignment offers a more concise coding method

module LOGIC_1 (port listing…) ;

...
wire OUT1;
...
assign OUT1 = A & B ;

alternativel module LOGIC_1 (port listing…) ;

y ...
wire OUT1 = A & B ;
...

Data Flow-Level Modeling - 10 - 7 © 2006 Xilinx, Inc. All Rights Reserved

 Outline
• Continuous Assignment
• Delay Specification
• Summary
• Appendix: Gate-Level
Modeling

Data Flow-Level Modeling - 10 - 8 © 2006 Xilinx, Inc. All Rights Reserved

 Gate Delays
• There are three delay parameters that can be specified to model gate
propagation

rise
1
0,x,z

1,x,z
fall
0

0,1,x turn off Z

Data Flow-Level Modeling - 10 - 9 © 2006 Xilinx, Inc. All Rights Reserved

 Simulating Delays
• Gate delays are listed immediately after the gate instantiation,
preceded by the “#” symbol
– If only one delay is listed, it will apply to all transitions

nand # 4 N1 ( OUT, IN_1, IN_2 ) ;

IN_1
IN_2

OUT

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Simulation Time

Data Flow-Level Modeling - 10 - 10 © 2006 Xilinx, Inc. All Rights Reserved

 Modeling Delays
• Gate delays are listed immediately after the gate instantiation,
preceded by the “#” symbol

– If three are listed, they will apply to

rise, fall, and turn-off respectively

nand # (2, 3, 5) N1 (OUT, IN_1, IN_2) ;

FYI: Any delay specification is ignored in synthesis

Data Flow-Level Modeling - 10 - 11 © 2006 Xilinx, Inc. All Rights Reserved

 Delay Specification
• Both regular and implicit assignment statements can include a delay
specification
– This models the propagation delay for the gate; ignored during synthesis

wire # 5 OUT1;
. . . A
assign OUT1 = A & B ; OUT1
B
alternatively
5 ns
wire # 5 OUT1 = A & B ;
or
wire OUT1 ;
assign # 5 OUT1 = A & B ;

Data Flow-Level Modeling - 10 - 12 © 2006 Xilinx, Inc. All Rights Reserved

 Structural and Data Flow Code
• Example
module COUNT3 ( input CLK, RST, output [2:0] Q) ;
wire N1, N2 ;
assign N1 = ( Q[0] ^ Q[1] ) ;
assign N2 = ( Q[2] ^ (Q[0] & Q[1])) ;
DFF DFF0 (~Q[0], CLK, RST, Q[0] ) ;
DFF DFF1 ( N1, CLK, RST, Q[1] ) ;
DFF DFF2 ( N2, CLK, RST, Q[2] ) ;
endmodule
module DFF ( input D, CLK, RST,
output reg Q ) ;
...

Data Flow-Level Modeling - 10 - 13 © 2006 Xilinx, Inc. All Rights Reserved

 “COUNT3” Implementation

Q0
DFF
Clk 0
Rst

N1 Q1
DFF1
Clk
assign N1 = ( Q[0] ^ Q[1] ) ; Rst

N2 Q2
DFF2
Clk
assign N2 = ( Q[2] ^ (Q[0] & Q[1])) ; Rst

Data Flow-Level Modeling - 10 - 14 © 2006 Xilinx, Inc. All Rights Reserved

 Outline
• Continuous Assignment
• Delay Specification
• Summary
• Appendix: Gate-Level
Modeling

Data Flow-Level Modeling - 10 - 15 © 2006 Xilinx, Inc. All Rights Reserved

 Knowledge Check
• What is wrong with the following example and how would you fix it?
Is it synthesizable?

– reg CS, RD, WR;

– assign #2 CS <= ADDR[10] & ADDR[9] & ~ADDR[8] & ~ADDR[7];
– always @ (posedge CLK )
– begin
–             assign #2 RD = ADDR[11] & CS;
– assign #2 WR = ~ADDR[11] & CS;
– end

Data Flow-Level Modeling - 10 - 16 © 2006 Xilinx, Inc. All Rights Reserved

 Answer
• The previous example contained incorrect usage of wire and reg

– wire CS;
– reg RD, WR;
– assign #2 CS = ADDR[10] & ADDR[9] & ~ADDR[8] & ~ADDR[7];
– always @ ( posedge CLK )
– begin
–             RD <= #2 ADDR[11] & CS;
– WR <= #2 ~ADDR[11] & CS;
– end

Data Flow-Level Modeling - 10 - 17 © 2006 Xilinx, Inc. All Rights Reserved

 Knowledge Check
• Which of the following operators can be used in an assign statement?
– (A) Logical and ( && )
– (B) Bitwise and ( & )
– (C) Reduction xor ( ^ )
– (D) All of the above

• When will a continuous assignment be evaluated or re-evaluated?

– (A) At the start of simulation only
– (B) Whenever an input signal changes value
– (C) When the target is re-assigned
– (D) On the leading edge of the clock signal

• Are data flow constructs with delay specifications synthesizable?

Data Flow-Level Modeling - 10 - 18 © 2006 Xilinx, Inc. All Rights Reserved

 Answers
• Which of the following operators can be used in an assign statement?
– (A) Logical and ( && )
– (B) Bitwise and ( & )
– (C) Reduction xor ( ^ )
– (D) All of the above

• When will a continuous assignment be evaluated or re-evaluated?

– (A) At the start of simulation only
– (B) Whenever an input signal changes value
– (C) When the target is re-assigned
– (D) On the leading edge of the clock signal

• Are data flow constructs with delay specifications synthesizable?

– Yes, the construct itself can be synthesized, but the delay specifications
will be ignored for synthesis

Data Flow-Level Modeling - 10 - 19 © 2006 Xilinx, Inc. All Rights Reserved

 Summary
• Data flow modeling describes combinatorial logic
• Continuous assignment statements are evaluated whenever a signal in
the expression changes value
• The implicit assignment statement combines an internal signal
declaration and a continuous assignment
• Assignment statements can include a delay specification for behavioral
simulation

Data Flow-Level Modeling - 10 - 20 © 2006 Xilinx, Inc. All Rights Reserved

 Where Can I Learn More?
• Application Notes at www.xilinx.com/support/mysupport.htm
– Select the Documentation tab
• Information at www.accellera.org
– Standards group for VHDL and Verilog
• Multimedia HDL training at www.technically-speaking.com
– Verilog and VHDL multimedia training products

• Verilog textbooks and references

– Starter’s Guide to Verilog 2001, Mike Cilletti, Prentice Hall, ISBN 0-13-141556-5
– Verilog 2001, A Guide…, Stuart Sutherland, KLUWER, ISBN 0-7981-2806-6
– Verilog HDL by Samir Palnitkar, Prentice Hall ISBN: 0-13-451675-3
– Verilog Designer’s Library by Bob Ziedman, Prentice Hall ISBN:0-13-081154-8
– HDL Chip Design by Douglas J. Smith, Doone Publications, ISBN:0-9651934-3-8

Data Flow-Level Modeling - 10 - 21 © 2006 Xilinx, Inc. All Rights Reserved

 Outline
• Continuous Assignment
• Delay Specification
• Summary
• Appendix: Gate-Level Modeling

Data Flow-Level Modeling - 10 - 22 © 2006 Xilinx, Inc. All Rights Reserved

 Gate-Level Modeling
• Gate-level modeling in Verilog uses predefined primitives. It is
straightforward and intuitive
– It is also very detailed in nature, and thus only suitable for small modules

FYI: Any gate-level model can be synthesized, but the actual gates used
depend on the available primitives and macros in the target technology
library

Data Flow-Level Modeling - 10 - 23 © 2006 Xilinx, Inc. All Rights Reserved

 Gate Types
• Verilog predefines the following n-input gate-level primitives:

and nand

or nor

xor xnor

Data Flow-Level Modeling - 10 - 24 © 2006 Xilinx, Inc. All Rights Reserved

 Buffers and Inverters
• For “buf,” “not,” and most standard gates, inputs of unknown “x” or high
impedance “z” usually produce an unknown output in simulation

buf not

Data Flow-Level Modeling - 10 - 25 © 2006 Xilinx, Inc. All Rights Reserved

 Buffer and Inverter with Enable
• Used for driving onto common outputs
bufif1 notif1

bufif0 notif0

FYI: Should be coded for mutual exclusivity; for example, ensuring that only
one driver is enabled at a time

Data Flow-Level Modeling - 10 - 26 © 2006 Xilinx, Inc. All Rights Reserved

 Gate Coding
• Instance names are optional
module AND_OR ( input A, B, C,D, output Z );
wire SIG1, SIG2 ;

and A1 ( SIG1, A, B ) ;
and A2 ( SIG2, C, D ) ;
or O1 ( Z, SIG1, SIG2 ) ;
....
endmodule
A SIG1
Gate output B
Z
must be listed first! C
D SIG2

Data Flow-Level Modeling - 10 - 27 © 2006 Xilinx, Inc. All Rights Reserved

 Coding Gates
• Gate primitives are referenced by their keyword identifiers, along with the
output and input signals

bufif0
IN_1 OUT_1

CTRL

bufif0 B1 ( OUT_1, IN_1,

CTRL ) ;

Data Flow-Level Modeling - 10 - 28 © 2006 Xilinx, Inc. All Rights Reserved

 Other Considerations
• Gates can be described with more than two inputs

and A0 ( OUT_1, IN1, IN2, IN3... ) ;

• Buffer and inverters can have multiple outputs

buf B1 ( OUT_1, OUT_2, IN1 ) ;

Data Flow-Level Modeling - 10 - 29 © 2006 Xilinx, Inc. All Rights Reserved