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Fpga 1

The document discusses Field Programmable Gate Arrays (FPGAs). It describes how FPGAs are chips that can be configured by customers after manufacturing to implement logic functions. It explains the architecture of FPGAs includes configurable logic blocks, interconnects, and input/output blocks. Finally, it outlines some applications of FPGAs like implementing ASICs and system on a chip designs.

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Amir Qureshi
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58 views29 pages

Fpga 1

The document discusses Field Programmable Gate Arrays (FPGAs). It describes how FPGAs are chips that can be configured by customers after manufacturing to implement logic functions. It explains the architecture of FPGAs includes configurable logic blocks, interconnects, and input/output blocks. Finally, it outlines some applications of FPGAs like implementing ASICs and system on a chip designs.

Uploaded by

Amir Qureshi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Wednesday, December 8, 2021

FPGA
FPGA stands for Field Programmable Gate Array.

Chips that are configured by the customer after


the manufacturing.

Have a similar structure to Programmable Array


Logic (PALs)

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Field Programmable Gate Arrays
 Structured very much like a gate array ASIC.

 Used to get market quickly regardless of cost.

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Complex Programmable Logic Device
 Consist of a number of PLDs in the same package.

 Can be programmed in a number of different languages.

 Electrically erasable and reprogrammable.

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Differences between CPLDs and FPGAs

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FPGA Architecture

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FPGA Architecture
Consists of:
Configurable Logic Blocks
Configurable I/O Blocks
Programmable interconnect
Clock circuitry
ALU’s
Memory
Decoders
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Characteristics of FPGA
Re-programmable
Switch Technology
More Power Consumption
High Production Cost
Low Design Density
Low Development Effort

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FPGA Technologies
Antifuse FPGAs

Flash FPGAs

SRAM FPGAs

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Antifuse Technology
Can be programmed once.

Manufactured by Quicklogic.

Configured by burning a set of fuses.

Updates Possible…. Bugs fixed.

ASIC replacement
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Flash Technology
Can be programmed several times.

Manufactured by Actel.

Updates Possible.

Expensive.

Non-volatile.
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SRAM Technology
Can be programmed Dynamically.
Manufactured by Actel, Altera, Atmel, Cyprea,
Lucent, Xilinx.
Current Technology.
Unlimited Programming.
Re-configuration is very fast.

Wednesday, December 8, 2021


SPARTAN - III
Family of FPGA.
Families differ in context of:
Architecture
Feature set
Families are similar in context of:
Flexibility
Programmable architecture of CLB’s.
Programmable I/O Blocks.
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Applications of FPGA
 Application Specific Integrated Circuits
 System on chip
 Implementation of Random Logic
 Replacement of SSIC for Random Logic
 FPGA based Compute Engines

This has major advantages for electronics companies in


terms of cost, reliability, reusability of intellectual
property, and time to market
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Practical Overview of FPGA Kit
VHDL program can be finally implemented to FPGA
Kit by the process of Synthesis.

Synthesis:
Automatic method of converting a higher level of
abstraction to a lower level of abstraction.

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Abstraction

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Synthesis Process

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Synthesis Process

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To synthesize: we require

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To Burn A Program

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After Generating Program file
Attach the FPGA kit with your computer.

Click on configure device option below the Generating


Program file option.

Open the program you want to burn on FPGA kit.

*.bit file will be created and your program will be


implemented on FPGA kit.
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Wednesday, December 8, 2021
LOGIC OPTIMIZATION TECHNIQUES
Optimization refers to choosing the best element from
some set of available alternatives.

All logic synthesis software provides the capability to


optimize a circuit for area and speed.

Few Provide power optimization also.

Further a design based optimization called resource


sharing is also provided.
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Optimization Techniques

Area Optimization.

Speed Optimization.

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Area Optimization
Early techniques addressed simple matrix-based
manipulation for Boolean algebra.
Later developments incorporated optimizations
based on don’t care conditions.
The optimization may be a general purpose one or
targeted at particular structures.
Underlying technology strongly affects the
optimization.
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Speed Optimization
 A common approach is to identify the critical path and to work on
reducing that.
 A simple optimization might be to replace each component on the
critical path with a higher rated but functionally equivalent
component from the library.
 Other optimization techniques might be able to strip out strings of
inverters from a design.
 Speed optimization is usually applied after area optimization.

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Similar Devices in wild:
As the timeline follows,
GAL:Gate Array Logic
 Simple arrays of logic gates
PLD:Programmable Logic Devices
 First programmable devices
EPLD:Electrically Programmable Logic Device
 Erasable programmable devices

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Similar Devices:
FLGA:Field Logic Gate Array
 Realtime configurable gate arrays
DRAM:Dynamic Random Access Memory
 Dynamic memory configurations.

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