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    Mini Project Presentation 17C45A0442

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    Shiva Tejaswini Paka
    The document discusses a proposed error detection technique for a median filter implemented in hardware on an FPGA. The technique checks if the median output value is within a dynamic range of the remaining non-median outputs to detect errors. It aims to protect the median filter from configuration memory bit flips caused by single event upsets, while having lower resource overhead than full redundancy techniques. Simulation results showed the technique could detect over 91% of corrupted images and minimize damage propagation to subsequent image processing.

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    Mini Project Presentation 17C45A0442

    Uploaded by

    Shiva Tejaswini Paka
    22 views13 pages
    The document discusses a proposed error detection technique for a median filter implemented in hardware on an FPGA. The technique checks if the median output value is within a dynamic range of the remaining non-median outputs to detect errors. It aims to protect the median filter from configuration memory bit flips caused by single event upsets, while having lower resource overhead than full redundancy techniques. Simulation results showed the technique could detect over 91% of corrupted images and minimize damage propagation to subsequent image processing.

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    Error detection using median filter.the mini project which we has done based on vlsi.

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    Mini%20Project%20Presentation%20%2017C45A0442

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    The document discusses a proposed error detection technique for a median filter implemented in hardware on an FPGA. The technique checks if the median output value is within a dynamic range of the remaining non-median outputs to detect errors. It aims to protect the median filter from configuration memory bit flips caused by single event upsets, while having lower resource overhead than full redundancy techniques. Simulation results showed the technique could detect over 91% of corrupted images and minimize damage propagation to subsequent image processing.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    22 views13 pages

    Mini Project Presentation 17C45A0442

    Uploaded by

    Shiva Tejaswini Paka
    The document discusses a proposed error detection technique for a median filter implemented in hardware on an FPGA. The technique checks if the median output value is within a dynamic range of the remaining non-median outputs to detect errors. It aims to protect the median filter from configuration memory bit flips caused by single event upsets, while having lower resource overhead than full redundancy techniques. Simulation results showed the technique could detect over 91% of corrupted images and minimize damage propagation to subsequent image processing.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 13

    Mini project Presentation on

    ERROR DETECTION TECHNIQUE


    FOR A MEDIAN FILTER

    Presented By
    P. Shiva tejaswini(17C45A0432)
    A. Mounika(17C45A0443) Under guidance of
    M. Saikiran(17C45A0442)
    A. Thriveni(17C45A0430) MD. Hameed pasha
    Associate Professor & Head, ECE

    DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


    JAYAMUKHI INSTITUTE OF TECHNOLOGICAL SCIENCE
    (An Autonomous Institute, Accredited by NBA, Affiliated to JNTUH)
    ,
    Narsampet Warangal – 506 332(T.S)
    Content
     Abstract
     Introduction
    •About project
    •About VLSI
     Objectives of project
     Methodology

    •Existing method

    •Proposed technique

     Outcome of the project

     Conclusion

     Questions and answers


    Abstract
     In digital image processing systems, the acquisition stage may
    capture impulsive noise along with the image. This physical
    phenomenon is commonly referred to as “salt-and pepper” noise.
    The median filter is a nonlinear image processing operation used
    to remove this impulsive noise from images. This digital filter can
    be implemented in hardware to speed up the algorithm. However,
    an SRAM-based FPGA implementation of this filter is then
    susceptible to configuration memory bit flips induced by single
    event upsets (SEUs), so a protection technique is needed for
    critical applications in which the proper filter operation must be
    ensured. In this project, a fault-tolerant implementation of the
    median filter is presented and studied in depth. Our protection
    technique checks if the median output is within a dynamic range
    created with the remaining non-median outputs. An output error
    signal is activated if a corrupted image pixel is detected, then, a
    partial or complete reconfiguration can be performed to remove
    the configuration memory error.

    Keywords:SRAM,FPGA,SEU,median filter
    INTRODUCTION
    To avoid corruption in the data stored in the
    memory, error correction codes(ECCs) are commonly
    used. ECCs add parity check bits to each memory
    word to detect and correct errors. This requires an
    encoder to compute those bits when writing to the
    memory and a decoder to detect and correct errors
    when reading from the memory. These elements
    increase the memory area and the power consumption,
    and also reduce the access speed. The proposed
    Decoder has been implemented in hardware
    description language and mapped to a 65- nm
    technology to show its benefits. The main contribution
    of this brief is to enable a fast and efficient parallel
    correction of the single and double-adjacent errors in
    the (24,12)Go lay code.
    Introduction to VLSI
     Very-large-scale integration (VLSI) is the process of
    creating integrated circuits by combining thousands of
    transistor-based circuits into a single chip. VLSI began
    in the 1970s when complex semiconductor and
    communication technologies were being developed. The
    microprocessor is a VLSI device. The term is no longer
    As common as it once was, as chips have increased in
    complexity into the hundreds of millions of transistors.
    This is the field which involves packing more and more
    logic devices into smaller and smaller areas.
    Design/manufacturing is extremely small. Applications
    wide ranging: most electronic logic devices.
    Objectives
    1. Image sensors often acquire undesirable noise along with the
    captured image frame, so it is important to repair these
    corrupted pixels to facilitate subsequent image processing
    operations such as edge detection or object recognition.
    2. In order to remove this noise, image filtering and
    enhancement is usually performed immediately after the
    image is captured and before any other image processing
    operation.
    3. SRAM-based FPGAs provide high performance, high
    densities, and low cost, while allowing a practically
    unlimited number of reconfigurations.
    4. Acquisition noise in digital image processing systems may
    be composed of impulsive noise such as hot and dead pixels.
    5.The term “hot pixels” describes those pixels that
    are much brighter than surrounding pixels, and
    term ”dead pixels” refers to those permanently
    off.
    6.When both physical phenomena appear together
    in the same image they are commonly referred to
    as “salt-and-pepper” noise.
    7.They are mainly caused by charge leakages within
    the image sensor chip.
    8.The median filter can efficiently attenuate the
    effects of low percentages of this ” salt-and-
    pepper” noise while preserving the edges of the
    objects existing in the image.
    Existing method
     Redundancy based techniques such as dual modular
    redundancy (DMR) or reduced precision redundancy
    (RPR) are typically used to protect digital filter. The
    main difference between these techniques is that the
    RPR method combines the main circuit with a low
    precision replica to detect errors in the most
    significant bits (MSBs), instead of using a full
    precision replica as happens in the DMR scheme. This
    means that least significant bits (LSBs) changes cannot
    be detected with RPR, but less resource overhead is
    added.
    Proposed technique
    Outcome of project
    CONCLUSIONS
     This project is an extension of work presented
    in about a fault-tolerant implementation of the
    median filter. Our proposed technique checks if
    the median output value is within a dynamic
    range created each time with the remaining
    non-median outputs. The proposed technique
    has been compared in terms of resource
    utilization and error detection rate with DMR
    and RPR schemes. The design has been
    implemented in a Xilinx SRAM-based FPGA
    and several fault-injection campaigns have
    been performed.
     Pixel-level results show that images with
    homogeneous pixel-value regions are less susceptible
    to be corrupted when processed by a configuration
    memory damaged median filter. More homogeneous
    pixel-value regions imply more median filter inputs
    with equal values, so the probability that a median
    filter malfunction alters the median value is
    decreased.Although our technique cannot detect as
    many corrupted pixels as the DMR scheme,it detects
    enough to prevent 91percent of the corrupted images
    being erroneously processed by the next image
    processing module.Moreover,the remaining 9 percent
    of undetected images present a lower MSE value than
    the DMR,which means that the image damage
    propagation to successive image processing
    operations is minimised.

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