AMBA AHB5 Feb - 1
AMBA AHB5 Feb - 1
AMBA AHB5 Feb - 1
ANUJ
AMBA: ADVANCED MICROCONTROLLER
BUS ARCHITECTURE
• This bus should be able to sustain the external memory bandwidth, on which The
CPU, on-chip memory and other DMA devices reside.
• This bus provides a high-bandwidth interface between the elements to carry out
majority of transfers.
• Also located on this high performance bus is a bridge to the lower bandwidth bus
(For e.g. APB), where most of the peripheral devices in the system are located.
AMBA BASED SYSTEM
AHB – ADVANCED HIGH-PERFORMANCE
BUS
• What is AHB ? ?
• Features:
• Burst Transfers
• Single-clock edge operation
• Wide data bus configurations, 64, 128, 256, 512, 1024 bits
SINGLE MASTER AHB SYSTEM BLOCK
DIAGRAM
AHB MASTER
INTERFACE
AHB SLAVE
INTERFACE
OPERATION
PROTOCOL SIGNALS
• Global Signals
• HCLK, HRESETn
• Master Signals
• HADDR[31:0], HBURST[2:0], HMASTLOCK, HPROT[3:0], HPROT[6:4], HSIZE[2:0], HTRANS[1:0],
HWDATA[31:0], HWRITE
• Slave Signals
• HRDATA[31:0], HREADYOUT, HRESP
• MUX Signals
• HRDATA[31:0], HREADY, HRESP
READ AND WRITE
TRANSFERS
1. Basic Transfers
• Address and Data Phase
0b01 BUSY
0b10 NONSEQ
0b11 SEQ
TRANSFER
TYPES
LOCKED
TRANSFERS
• Important protocol signal involved – HMASTLOCK
• During an undefined length burst, INCR, the master might insert BUSY
transfers and then decide that no more data transfers are required.
• Under these circumstances, it is acceptable for the master to then perform a NONSEQ
or IDLE transfer that then effectively terminates the undefined length burst.
INCR
INCR4
INCR8
WRAP4
WRAP8
WAITED TRANSFER
• Slaves use HREADYOUT to insert wait states if they require
more time to provide or sample the data.
• During a waited transfer, the master is restricted to what
changes it can make to the transfer type and address.
• Transfer type changes during wait states.
• Address changes during wait states
TRANSFER TYPE CHANGES DURING
WAIT STATES
• IDLE Transfer
• During a waited transfer, the master is permitted to change the transfer type
from IDLE to NONSEQ. When the HTRANS transfer type changes to NONSEQ
the master must keep HTRANS constant, until HREADY is HIGH.
• BUSY transfer, fixed length burst
• During a waited transfer for a fixed length burst, the master is permitted to
change the transfer type from BUSY to SEQ. When the HTRANS transfer type
changes to SEQ the master must keep HTRANS constant, until HREADY is
HIGH.
• BUSY transfer, undefined length burst
• During a waited transfer for an undefined length burst, INCR, the master is
permitted to change from BUSY to any other transfer type, when HREADY is
LOW. The burst continues if a SEQ transfer is performed but terminates if an
IDLE or NONSEQ transfer is performed.
ADDRESS CHANGES DURING WAIT
STATES
• During an IDLE transfer
• RESET
• The reset signal, HRESETn, is the only active LOW signal in the protocol and
is the primary reset for all bus elements.
• The reset can be asserted asynchronously, but is deasserted synchronously
after the rising edge of HCLK.
• During reset all masters must ensure the address and control signals are at
valid levels and that HTRANS[1:0] indicates IDLE.
• During reset all slaves must ensure that HREADYOUT is HIGH.
THANK
YOU