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Jnana Sahyadri: Under The Guidence of Submitted by

This document summarizes the architecture and features of the Intel 80386 microprocessor. It discusses how the 80386 was developed to address limitations of the 16-bit 80286 by incorporating 32-bit processing. The 80386 has a 32-bit external data bus and memory address bus, allowing it to access up to 4GB of memory. It also has faster processing speeds of up to 20 million instructions per second. The document describes the internal architecture of the 80386 including the central processing unit, memory management unit, and bus interface unit. It provides details on the 80386's 32-bit register set and new segment registers.

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53 views12 pages

Jnana Sahyadri: Under The Guidence of Submitted by

This document summarizes the architecture and features of the Intel 80386 microprocessor. It discusses how the 80386 was developed to address limitations of the 16-bit 80286 by incorporating 32-bit processing. The 80386 has a 32-bit external data bus and memory address bus, allowing it to access up to 4GB of memory. It also has faster processing speeds of up to 20 million instructions per second. The document describes the internal architecture of the 80386 including the central processing unit, memory management unit, and bus interface unit. It provides details on the 80386's 32-bit register set and new segment registers.

Uploaded by

Vagi Gowda
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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JNANA SAHYADRI

Shankaraghatta

Under the Guidence of


Shashidhar sir
Lecturer Submitted By
Department of Electronics Seema
Jnana sahyadri Second sem M.Sc.
shankaraghatta Department of electronics
Jnana sahyadri
shankaraghatta
Contents
 Introduction
 Architecture of 80386
• Signal description of 80386
• Registors of 80386
• Reference
Introduction
80286 was a first processor to
incorporate the concepts of memory
management.The 16 bit word length of
80286 put limitations on it’s operating
speed.Thus the 32bit processor 80386
was born.The 32bit ALU allows to process
32bit data.It has 32bit address bus so it
can access upto 4GB.It runs with a speed
upto 20MHz instruction per second.
Architecture of 80386
The internal architecture of 80386 is
divided into three sections
Central processing unit
Memory management unit
Bus interface unit
The central processing unit is further divided into
execution unit and instruction unit.Execution unit it
has eight general purpose and eight special purpose
registers which are either used for handling data or
calculating offset address.The instruction unit
decodes the opcode bits received from the 16byte
instruction code queue.
Then arranges them in a 3 instruction decoded
instruction queue after decoding them so as to pass to the
control section for deriving the neccessary control signals.
Memory management unit: It consists of segmentation
unit and paging unit.The segmentation unit allows
segment of size 4GB at maximum.The paging unit works
under the control of segmentation unit i.e., each segment
is divided into pages.The paging unit converts linear
address into physical address.The control and attribute
PLA checks the previlages at the page level.The limit and
attribute PLA checks segment limit and attribute at
segment level to avoid invalid access to code and data in
the memory segment.
The bus control unit: It has a prioritizer to
resolve the priority of the various bus
requests the control access of the bus.The
address drives the bus enable and
address signals A0-A31.The pipeline and
dynamic bus sizing units handle the
related control signals.
Registers of 80386
The most important change in the 80386
was the introduction of 32bit register set.The
Ax,Bx,Cx,Dx,SI,DI,BP,SP,flags,IP registers
were all extended to 32bits.The 80386 calls
these new 32bit version EAX, EBX, ECX,
EDX, ESI, EDI, EBP, ESP, EFLAGS, EIP to
differentiate them from their 16bit
version.Besides these the 32bit version the
80386 also provide 2new 16bit segment
registers FS and GS these are the external
segment registers.
FLAG Registers(EFLAG)
The EFLAG registers contain 13flags
REFERENCE
A K Ray
 K M Bhurchandi

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