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HDL Descriptions

The document compares Verilog and VHDL languages. It discusses topics like comments, case sensitivity, numbers, operators and provides examples of structural modeling like a 4:1 multiplexer.

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Juan Pablo Marquez Echavarria

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0% found this document useful (0 votes)

13 views27 pages

HDL Descriptions

The document compares Verilog and VHDL languages. It discusses topics like comments, case sensitivity, numbers, operators and provides examples of structural modeling like a 4:1 multiplexer.

Uploaded by

Juan Pablo Marquez Echavarria

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

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Hardware Description

Languages
Comparison between Verilog and VHDL
Examples
Bitwise Operators
Bitwise Operators
Bitwise Operators
Comments
Verilog comments are just like those in C or Java. Comments beginning with /*
continue, possibly across multiple lines, to the next */. Comments beginning with
// continue to the end of the line.
Verilog is case-sensitive. xyz and XYz are different signals in Verilog.

VHDL comments begin with -- and continue to the end of the line. Comments
spanning multiple lines must use -- at the beginning of each line.
VHDL is not case-sensitive. xyz and XYz are the same signal in VHDL. However,
other tolos that may read your file might be case sensitive, leading to nasty bugs
if you blithely mix upper and lower case.
Reduction Operators
Reduction Operators
Conditional Assignment
Conditional Assignment
Conditional Assignment
Conditional Assignment
Internal Variables
Internal Variables
Operator Precedence (Verilog)
Operator Precedence (VHDL)
Numbers (Verilog)
Numbers (Verilog)
• Numbers are represented as:
<size>’<signed><radix>value //”<>” indicates optional part
• Size: The number of binary bits the number is comprised of. Not the number
of hex or decimal digits. Default is 32 bits.
• Signed: Indicates if the value is signed. Either s or S can be used.
• Not case dependent.
• Default is unsigned.
• Radix: Radix of the number
• ‘b or ‘B: binary
• ‘o or ‘O: octal
• ‘h or ‘H: hex
• ‘d or ‘D: decimal
• Default is decimal
Numbers (Verilog)
• If no prefix given, number is assumed to be 32-bit
• Verilog expands “value” to fill given <size> working from LSB to MSB.
• If <size> is smaller than “value”
• MSBs of “value” are truncated with warning (tool dependent)
Numbers (Verilog)
Format Prefix Legal characters
Binary ‘b 01xXzZ_?
Octal ‘o 0-7xXzZ_?
Decimal ‘d 0-9_
hexadecimal ‘h 0-9a-fA-FxXzZ_?

• The underscore “_” is a separator used to improve readability e.g.:

0010_1010_1110_0101 is easily read as 0x2AE5
• The character “x” or “X” represents unknown
• The character “z” or “Z” represents high impedance
• The character “?” represents high impedance, but it is also “don’t care”to
synthesis.
Numbers (VHDL)
Tristate Buffer
Concatenation
Type Conversion (VHDL)
Structural Model of 4:1 MUX
Structural Model of 4:1 MUX
Structural Model of 4:1 MUX

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HDL Descriptions

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HDL Descriptions

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Hardware Description

• The underscore “_” is a separator used to improve readability e.g.:

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