Why Synthesis tool?

• Normally if designs are small, custom

design will produce more efficient HW but
productivity will be really low.
• High-level design is less prone to human
error.
• High-level design is done without significant
concern about design constraints and
technology process.
• In this way, Logic synthesis tools allow
technology independent design & design
reuse.
 SYNTHESIS

• Automatic method of converting a higher level

of description of the design into an optimized
gate level description given standard cell library
(Technology library) and certain design
constraints

• Synthesis tools convert High Level descriptions

(HDL Description) into gate level netlists
 Gate level netlist synthesis
Standard cell
library – logic
Technology gates,
Library macrocells

High Level
Description Synthesis Gate Level
Netlist

VHDL,
Verilog Constraints

Timing,
Area,
Testability,
Power
SYNTHESIS PROCESS

VHDL RTL Description Created by user

Translate
Unoptimized Boolean
Description
Optimize

Optimized Boolean Created by

Description synthesis tool
Map to Gates

Gate Level Netlist

 Synthesis Process …

• Translation
– Converting from RTL Description to boolean
equivalent description

– IF, CASE, LOOP , Conditional signal

assignment statements, Selected signal
assignment statements are converted to their
boolean equivalent form.
 Synthesis Process…
• Boolean Optimization
– convert an unoptimized boolean description into optimized
boolean form
– Quine-McCluskey Algorithm was used earlier
– Presently Espresso heuristic logic minimizer is a standard
tool for optimization
– Logic optimization algorithms generally work either on the
structural (SOP) or functional representation of the circuit.
• Mapping to Gates
– Takes logically optimized boolean description created by
optimization step and uses logical and timing information
from technology library to build a netlist
 SYNTHESIS TOOLS
• Software tools for logic synthesis targeting ASICs
– Design Compiler by Synopsys
– Encounter RTL Compiler by Cadence Design System
– BuildGates an older product by Cadence Design System
– BlastCreate by Magma Design Automation
– BooleDozer Logic synthesis tool by IBM

• Software tools for logic synthesis targeting FPGAs

– Encounter RTL Compiler by Cadence Design System
– Leonardo Spectrum and Precision (RTL/Physical) by Mentor
Graphics
– Synplify (PRO / Premier) by Synplicity
– BlastFPGA by Magma Design Automation
– Quartus II integrated Synthesis by Altera
– XST (delivered within ISE) by Xilinx
– DesignCompiler Ultra and IC Compiler by Synopsys
– IspLever by Lattice Semiconductor
 Synthesis from VHDL /
VERILOG
1. Layout synthesis
2. Logic synthesis
3. RTL synthesis
4. High Level Synthesis
5. System Synthesis
 Coding for Synthesis
 VHDL and Verilog are hardware description
languages and simulation languages that were not
originally intended as inputs to synthesis.

 Therefore, many hardware description and

simulation constructs are not supported by
synthesis tools.

 VHDL and Verilog semantics are well defined for

design simulation. The synthesis tools must
adhere to these semantics to ensure that designs
simulate the same way before and after synthesis.
 Guidelines to be followed to create code that
simulates the same way before and after synthesis.

1. Omit the Wait for Statement

 eg. Wait for 20 ns; - VHDL construct

 # 20 ns; - Verilog construct

• This statement does not synthesize to a component.

In order to describe a similar “wait-for-time effect” that
can be synthesized, we need to describe it as an FSM
state that self-loops until a counter (set or reset at an
earlier state) reaches a count value that translates to
the desired wait time needed (Count value decided
based on the clock speed).
2. Omit the ...After clause or Delay Statement

 ...After XX ns statement in VHDL code.

 Delay assignment in Verilog code.

eg.
• Q <=0 after 20 ns; - VHDL
• assign #20 Q=0; - Verilog

• These statements are usually ignored by the synthesis

tool.
3. Omit Initial Values
 Do not assign signals and variables initial
values because initial values are ignored
by most synthesis tools.

• Eg. do not use initialization statements

like
• signal sum : integer := 0; - VHDL
• initial sum = 1’b0; - Verilog
4. Order and Group Arithmetic Functions

• The ordering and grouping of arithmetic functions can influence

design performance.
eg. ADD1 <= A1 + A2 + A3 + A4; -Statement 1
ADD1 <= (A1 + A2) + (A3 + A4); -Statement 2

• The first statement cascades three adders in series.

• The second statement creates two adders in parallel: A1 + A2

and A3 + A4. In the second statement, the two additions are
evaluated in parallel and the results are combined with a third
adder.

• RTL simulation results are the same for both statements,

however, the second statement results in a faster implementation
5. Don’t Mix positive and negative edge
triggered flipflops in a design
It may introduce inverters and buffers in
the clock tree. This can add clock skews
in the circuit.