Digital Design – CSE202

Module-2
Fundamentals of Digital System
Design
(Magnitude Comparator, Decoder, Encoder,
Multiplexer, Demultiplexer)
Magnitude Comparator
• Combinational circuit that compares two numbers A and B
and determines their relative magnitudes.
• For two inputs A and B, there are three output terminals
for the conditions A > B, A = B and A < B.
1- bit Magnitude Comparator
Inputs Outputs
A B A<B A=B A>B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
2- bit Magnitude Comparator
INPUTS OUTPUT
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
2- bit Magnitude Comparator
2- bit Magnitude Comparator
4-bit Magnitude Comparator
Decoders
• Converts binary information from n input lines to a
maximum of 2n unique output lines.
• If the n bit coded information has unused combinations,
the decoder may have fewer than 2n outputs. The decoder is
called n-to-m-line decoder, where m≤ 2n
2-to-4 line Decoder
2-to-4 line Decoder
Inputs Outputs
X Y D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
3-to-8-line Decoder
• Three inputs are decoded into eight outputs, each
representing one of the minterms of the three input variable
• Application – Binary to Octal conversion

3× 8
Decoder
Truth Table
Inputs Outputs

X Y Z D0 D1 D2 D3 D4 D0 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Circuit Diagram
2-to-4-line Decoder with enable
input(Active LOW output)
2-to-4-line Decoder with enable input
• The circuit operates with complemented outputs and
complement enable input.
• Decoder will be enables when E is 0 and will be disabled when
E is 1.
• Only one output can be 0 at any given time.
 4 ×16 decoder using two 3 × 8
decoders
• When w = 0,top decoder will be enabled
and other is disabled. Minterms from 0000
to 0111 will be generated.
• When w = 1, bottom decoder will be
enabled and generates minterms from
1000 to 1111.Output of top decoder are all
0’s.
Implementation of a Full Adder with
a Decoder

S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7)
 4 ×16 decoder using two 3 × 8
decoders
W X Y Z
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
W=0
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
W=1 1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
 Exercises
Using a decoder and external gates,design the combinational
circuit defined by the Boolean functions, F1 = x’yz’ + xz, F2 = xy’z’
+ x’y, F3 = x’y’z’ + xy.
 Exercises
Construct a 5-to-32 line decoder with four 3-to-8 line decoders with
enable and a 2-to-4 line decoder.
Encoders
• Encoder has 2n(or fewer) input lines and n output lines.
• Performs inverse operation of decoder
• Eg : Octal – to – binary encoder
• It is assumed that only one input can be active at any given
time.
Octal-to-Binary Encoder

A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7
Octal-to-Binary Encoder
Ambiguities
• If two inputs are active simultaneously, output produces an
undefined combination.
Eg : If D3 and D6 are 1 simultaneously, output will be
111which is neither binary 3 nor binary 6.
Solution : Establish an input priority in encoder circuits to
ensure that only one input is encoded.
• Output will be all 0’s when
1. all inputs are zeros
2. D0 equals 1
Solution : Provide one more output to indicate whether at
least one input is equal to 1.
Priority Encoder
• Includes priority function
• If two or more inputs are equal to 1 at the same time,
the input having the highest priority will take
precedence.
• Higher the subscript number, higher the priority of
inputs
• Valid bit indicator(V) is set to 1when one or more
inputs are 1.
• Outputs are not inspected when V is 0.
• ‘X’ in input represents truth table in condensed form
Eg : X100 represents 0100 and 1100
Four-input Priority Encoder
Four-input Priority Encoder

V = D0 + D1 + D2 + D3
Four-input Priority Encoder
Multiplexers
• Selects binary information from one of
many input lines and directs it to a single
output line.
• 2n input lines + n selection lines  Single
output line
2 × 1 Multiplexer
SEL OUT
0 IN1 OUT = (SEL)’(IN1) + (SEL)(IN2)
1 IN2

1
4 × 1 Multiplexer
Quadruple 2-to-1 Line Multiplexer
 Boolean function implementation
• Minterms of a Boolean function of ‘n’
variables can be generated in a multiplexer
that has ‘n’ selection inputs and 2n data
inputs(one for each minterm).
• Also possible to implement a Boolean
function of n variables with a multiplexer
that has n-1 selection inputs.
First n-1 variables of the function are connected
to selection inputs
Remaining single variable is used as data input
MAP ENTERED VARIABLE(MEV) TECHNIQUE

• K Map becomes difficult to manage when

number of variables exceed 5 or 6.
• MEV is used to increase the effective size
of k-map.
• It allows a smaller map to handle large
number of variables.
• This is done by writing output in terms of
input.
RULES FOR ENTERING VALUES IN MEV-MAP
Rule Map
MEV Function Comments
No. Entry
0 0 If f = 0 for both values of MEV, enter 0 in
1 0
1 0 appropriate cell of MEV Map
0 1 If f = 1 for both values of MEV, enter 1 in
2 1
1 1 appropriate cell of MEV Map
0 0 If f = MEV for both values of MEV, enter MEV
3 MEV
1 1 in appropriate cell of MEV Map
0 1 If f is complement of MEV, enter MEV in
4 MEV
1 0 appropriate cell of MEV Map
0 x If f = x for both values of MEV, enter x in
5 x
1 x appropriate cell of MEV Map
0 x If f = x for MEV = 0 and f = 0 for MEV = 1,
6 0
1 0 enter 0 in appropriate cell of MEV Map
0 0 If f = 0 for MEV = 0 and f = x for MEV = 1,
7 0
1 x enter 0 in appropriate cell of MEV Map
0 x If f = x for MEV = 0 and f = 1 for MEV = 1,
8 1
1 1 enter 1 in appropriate cell of MEV Map
0 1 If f = 1 for MEV = 0 and f = x for MEV = 1,
9 1
1 x enter 1 in appropriate cell of MEV Map
Boolean function implementation
4-input function with a multiplexer
Demultiplexers
• Takes a single input line and routes it to
one of several digital output lines.
• A demultiplexer of 2n outputs has n select
lines.
• Decoder with enable input can function
as a demultiplexer
1-to-2 DEMUX
1-to-4 DEMUX
1-to-8 DEMUX
 Exercises
• Construct 16 ×1 Multiplexer with two 8 × 1 and
one 2 ×1 multiplexers.
 Exercises
Implement Boolean function gates.F(A,B,C,D) = ∑(1,3,4,11,12,13,14,15)
with 4 ×1 multiplexer and external gates.