8085 - INTERRUPTS

• In many real-time operations, the microprocessor should be able to receive an external

asynchronous signal (interrupt) while it is running a routine. An interrupt is considered to be
an emergency signal that may be serviced. The Microprocessor may respond to it as soon as
possible.

• Interrupt is a process where an external device can get the attention of the microprocessor.
• The process starts from the I/O device
• The process is asynchronous

• What happens when MP is interrupted ?

• When the Microprocessor receives an interrupt signal, it suspends the currently
executing program and jumps to an Interrupt Service Routine (ISR) to respond to the
incoming interrupt.
• Each interrupt will most probably have its own ISR.

Interrupts •

•
An interrupt is a hardware-initiated subroutine CALL.

When the interrupt signal arrives:

• The processor will break its routine
• Go to a different routine (service routine)
• Complete the service routine
• Go back to the “regular” routine

• In order to execute an interrupt routine, the processor:

• Should be able to accept interrupts (interrupt enable)
• Save the last content of the program counter (PC)
• Know where to go in program memory to execute the service routine
• Tell the outside world that it is executing an interrupt
• Go back to the saved PC location when finished.
Interrupts in 8085
INTA

Main routine

Interrupt

Save Send out

program Disable interupt
counter interrupts acknowledge

Go to
service
Go back
routine

Get
original RET
program
counter Service routine
Interrupt processing flow
Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC
Responding to
Interrupts
• Responding to an interrupt may be immediate or
delayed depending on whether the interrupt is
maskable or non-maskable and whether interrupts
are being masked or not.
• There are two ways of redirecting the execution to
the ISR depending on whether the interrupt is
vectored or non-vectored.
• Vectored: The address of the subroutine is
already known to the Microprocessor
• Non Vectored: The device will have to supply
the address of the subroutine to the
Microprocessor
The Purpose of Interrupts
• Interrupts are useful when
interfacing I/O devices with low
data-transfer rates, like a keyboard
or a mouse, in which case polling
the device wastes valuable
processing time
• The peripheral interrupts the normal
application execution, requesting to
send or receive data. Main Program

Printer Interrupt
Main Program

Modem Interrupt
Main Program

Modem Interrupt
Main Program

• The processor jumps to a special

program called Interrupt Service
Routine to service the peripheral
• After the processor services the
peripheral, the execution of the
interrupted program continues.
BASIC INTERRUPT TERMINOLOGY

Interrupt pins: Set of pins used in hardware interrupts

Interrupt Service Routine code used for handling a specific interrupt

(ISR) or Interrupt handler:

In systems with more than one interrupt inputs, some interrupts have a higher priority than other
Interrupt priority:
•They are serviced first if multiple interrupts are triggered simultaneously

Interrupt vector: Code loaded on the bus by the interrupting device that contains the Address (segment and offset) of specific interrupt service routine

Masking Interrupt Masking: Ignoring (disabling) an interrupt

Non-Maskable Interrupt Interrupt that cannot be ignored

Types of Interrupts
Interrupts can be classified into two Interrupts can also be classified into two Interrupts can be classified based on
types based on responding : types based on the addressing: initialization as:
• Maskable Interrupts • Vectored • Software Interrupts - Internal event
• Can be delayed or Rejected by the • The address of the service routine is (Software generated)
8085 hard-wired • Hardware Interrupts - External event
• Can be Enabled or Disabled by EI And • The address of the subroutine is
DI instruction already known to the Microprocessor
• Non-Maskable Interrupts • i.e. ISR will be at the pre-defined
• Can not be delayed or Rejected by the address
8085 • Non-vectored
• The address of the service routine
needs to be supplied externally by the
device
• The device will have to supply the
address of the subroutine to the
Microprocessor
• i.e. The ISR address to be defined
Maskable
and Non-
Maskable
Interrupts
 • For processor with multiple interrupt
input pins, the various interrupts are
assigned a priority.
• When simultaneous interrupts occur
the highest priority interrupt will be
Interrupt serviced before lower priority
interrupts.
Priority • It is possible to arrange software such
that whilst a lower priority interrupt is
being serviced that a higher priority
interrupt can interrupt the lower
priority service routine.
 Software Interrupts in the 8085 – RST
Instructions

• A software interrupt is a particular instructions that can be inserted into the desired location in the program. There are eight
Software interrupts in 8085 Microprocessor. From RST0 to RST7.
• RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7
• They allow the microprocessor to transfer program control from the main program to the subroutine program. After completing
the subroutine program, the program control returns back to the main program.
• We can calculate the vector address of these interrupts using the formula given below:
Vector Address = Interrupt Number * 8
• So we can find simply vector address. For Example:
• RST2: vector address=2*8 = 16
• RST5: vector address=5*8 = 40
 Software Interrupts in the 8085 – RST
Instructions

Binary Codes
Mnemonics HEX Address
D7 D6 D5 D4 D3 D2 D1 D0

RST0 1 1 0 0 0 1 1 1 C7 0000
RST1 1 1 0 0 1 1 1 1 CF 0008
RST2 1 1 0 1 0 1 1 1 D7 0010
RST3 1 1 0 1 1 1 1 1 DF 0018
RST4 1 1 1 0 0 1 1 1 E7 0020
RST5 1 1 1 0 1 1 1 1 EF 0028
RST6 1 1 1 1 0 1 1 1 F7 0030
RST7 1 1 1 1 1 1 1 1 FF 0038
 • The restart sequence is made up of three machine
cycles
• In the 1st machine cycle:
• The microprocessor sends the INTA signal.
• While INTA is active the microprocessor
reads the data lines expecting to receive,
The 8085 from the interrupting device, the opcode for
the specific RST instruction.
Software • In the 2nd and 3rd machine cycles:
• the 16-bit address of the next instruction is
Interrupt Process - saved on the stack.
• Then the microprocessor jumps to the
Restart Sequence address associated with the specified RST
instruction.

• See the Page 96, Figure 3.17, of your Text Book for the
Timing Diagram of the RST instruction
Hardware Generation of RST Opcode
• How does the external device produce the opcode for the appropriate
RST instruction?
• The opcode is simply a collection of bits.
• So, the device needs to set the bits of the data bus to the appropriate value in
response to an INTA signal.
+5v

1
1

bus
EF to data
1
0
1
1
1
1

Enabling RST5
 • During the interrupt acknowledge
machine cycle, (the 1st machine cycle
of the RST operation):
• The Microprocessor activates the
INTA signal.
Hardware • This signal will enable the Tri-state
buffers, which will place the value
Generation of EFH on the data bus.
• Therefore, sending the
RST Opcode Microprocessor the RST 5
instruction.

• The RST 5 instruction is exactly

equivalent to CALL 0028H
 • There are 5 interrupt inputs:
• TRAP (non maskable)
• RST7.5
• RST6.5
• RST5.5
• INTR
• The INTR input.
• The INTR input is the only non-vectored
Hardware interrupt.
Interrupts in • INTR is maskable using the EI/DI instruction
pair.
the 8085 • RST 5.5, RST 6.5, RST 7.5 are all automatically
vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.
• TRAP is the only non-maskable interrupt in the 8085
• TRAP is also automatically vectored
 Hardware Interrupts in the
8085

Maskable Non- Maskable

Non vectored Vectored

INTR RST 5.5 TRAP (vectored)
RST 6.5
RST 7.5
 • When a device interrupts, it actually wants the MP to
give a service which is equivalent to asking the MP to
call a subroutine. This subroutine is called ISR (Interrupt
Service Routine)
• INTR input is enabled when EI instruction is executed.
• The status of the RST 7.5, RST 6.5 and RST 5.5 pins are
Hardware determined by both EI instruction and the condition of
the mask bits in the interrupt mask register
Interrupts in • The ‘EI’ instruction is a one byte instruction and is used
to Enable the maskable interrupts.
the 8085 • The ‘DI’ instruction is a one byte instruction and is used
to Disable the maskable interrupts.
• The TRAP interrupt is a non-maskable interrupt i.e. not
affected by EI and DI instructions
 Hardware Interrupts
in the 8085

• INTR
Maskable • RST Vectored

Non-
• TRAP
Maskable

• RST5.5, RST6.5,
Vectored RST7.5, TRAP
Hardware Interrupts in the 8085
TRAP
RST7.5
RST6.5
RST 5.5 8085
INTR
INTA
 Hardware
Interrupts in
the 8085
 • An interrupt vector is a pointer
the memory location of an interrupt
handler, which prioritizes
interrupts and saves them in a queue
Interrupt • All interrupts (vectored) are mapped
onto a memory area called the
Vectors and Interrupt Vector Table (IVT).
• The IVT is usually located in
the Vector memory page 00 (0000H - 00FFH).
Table • The purpose of the IVT is to hold
the vectors that redirect the
microprocessor to the right place
when an interrupt arrives.
The 8085 Non-Vectored Interrupt Process
(INTR)
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If INTR is high, MP completes current instruction, disables the interrupt flip-flop and sends INTA
(Interrupt acknowledge) signal to the device that interrupted
4. INTA allows the I/O device to send a RST instruction through data bus.
5. Upon receiving the INTA signal, MP saves the memory location of the next instruction on the
stack and the program is transferred to ‘call’ location (ISR Call) specified by the RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt within the program.
8. RET instruction at the end of the ISR allows the MP to retrieve the return address from the
stack and the program is transferred back to where the program was interrupted.
 The 8085A processor executes a number of machine
cycles, in response to a non-vectored interrupt
(INTR), prior to execution of the first instruction of
the interrupt service routine.
Machine
Cycles with The processor completes the execution of the current
instruction. (Note : The processor only samples the
Non-Vectored interrupt inputs in the last T-state of the last machine
cycle in the current instruction cycle)
Interrupts
(INTR) This has implication in system design as it means that
the interrupt signal on INTR must remain in the
asserted state for at least the longest instruction in
the 8085A instruction set to guarantee that the
processor recognises the interrupt.
 The processor then executes a six T-state interrupt acknowledge
machine cycle ( the INTA machine cycle is similar to the opcode fetch
machine cycle except that the program counter is not incremented
and the INTA* control signal is asserted instead of RD*)

Machine In response to the INTA* signal, the interrupting device need to place
the opcode of an instruction onto the data bus ( called jamming ).

Cycles with
Non-Vectored The processor reads the opcode in the normal manner and stores it in
the instruction register.
Interrupts
(INTR) The choice of opcode is restricted as it is necessary to automatically
save the contents of the program counter to enable the program to
return to the point in the software where it was interrupted.
 The only viable choice of 8085A instruction is either the CALL
instruction or the RST n instruction.

Machine The CALL instruction is a 3-byte instruction with bytes 2 & 3

being the address of the first instruction of the subroutine ( in
Cycles with this case the interrupt service routine).

Non-Vectored Following decoding of the call opcode, the processor executes

a further two interrupt acknowledge machine cycles to fetch
Interrupts the address of the start of the ISR.

(INTR) - CALL It is incumbent on the interrupting device to place the low

byte of the address of the ISR onto the data bus in response to
the second INTA* control signal and the high byte of the
address in response to the third INTA* signal.
 The execution phase of the CALL instruction can now take place.

Machine The processor firstly executes two memory write machine cycles
to save the current contents of the program counter onto the

Cycles with stack. The address as to where in memory the contents of PC is to

be saved is specified by the stack pointer register.

Non-Vectored Finally the processor overwrites the contents of the program

counter with the second and third bytes of the call instruction.
Interrupts
(INTR) - CALL The next instruction the processor will execute will be the first
instruction of the ISR.
Machine Cycles with Non-Vectored Interrupts (INTR)

The processor then executes a six T-state interrupt acknowledge

machine cycle ( the INTA machine cycle is similar to the opcode fetch
machine cycle except that the program counter is not incremented and
the INTA* control signal is asserted instead of RD*)
29
Machine Cycles with Non-Vectored Interrupts (INTR)

In response to the INTA* signal, the interrupting device need to place

the opcode of an instruction onto the data bus ( called jamming ).
The processor reads the opcode in the normal manner and stores it in
the instruction register. 30
Machine Cycles with Non-Vectored Interrupts (INTR)

The choice of opcode is restricted as it is necessary to automatically

save the contents of the program counter to enable the program to
return to the point in the software where it was interrupted.
31
Machine Cycles with Non-Vectored Interrupts (INTR)

The only viable choice of 8085A instruction is either the CALL

instruction or the RST n instruction.
The CALL instruction is a 3-byte instruction with bytes 2 & 3 being the
address of the first instruction of the subroutine ( in this case the
32
interrupt service routine).
Machine Cycles with Non-Vectored Interrupts (INTR)

Following decoding of the call opcode, the processor executes a further

two interrupt acknowledge machine cycles to fetch the address of the
start of the ISR.

33
Machine Cycles with Non-Vectored Interrupts (INTR)

Low Byte in 2nd INTA

It is incumbent on the interrupting device to place the low byte of the

address of the ISR onto the data bus in response to the second INTA*
control signal and the high byte of the address in response to the third
INTA* signal.
34
Machine Cycles with Non-Vectored Interrupts (INTR)

High Byte in 3rd INTA

It is incumbent on the interrupting device to place the low byte of the

address of the ISR onto the data bus in response to the second INTA*
control signal and the high byte of the address in response to the third
INTA* signal.
The execution phase of the CALL instruction can now take place. 35
Machine Cycles with Non-Vectored Interrupts (INTR)

The execution phase of the CALL instruction can now take place.
The processor firstly executes two memory write machine cycles to
save the current contents of the program counter onto the stack. The
address as to where in memory the contents of PC is to be saved is
specified by the stack pointer register. 36
Machine Cycles with Non-Vectored Interrupts (INTR)

Finally the processor overwrites the contents of the program counter

with the second and third bytes of the call instruction.
The next instruction the processor will execute will be the first
instruction of the ISR.
37
 • How long must INTR remain high?
• The microprocessor checks the INTR
line one clock cycle before the last T-
state of each instruction.
• The INTR must remain active long
The 8085 Non- enough to allow for the longest
Vectored Interrupt instruction.
Process (INTR) - • The longest instruction for the 8085 is
the conditional CALL instruction which
Issues in requires 18 T-states.
Implementing INTR • Therefore, the INTR must remain active for
Interrupts 17.5 T-states.
• If f= 3MHZ then T=1/f and so, INTR must
remain active for [ (1/3MHZ) * 17.5 ≈ 5.8
micro seconds].
 • How long can the INTR remain high?
• The INTR line must be deactivated
The 8085 Non- before the EI is executed.
Otherwise, the microprocessor will
Vectored Interrupt be interrupted again.
Process (INTR) - • Once the microprocessor starts to
Issues in respond to an INTR interrupt, INTA
Implementing INTR becomes active (=0).
Interrupts
Therefore, INTR should be turned off as
soon as the INTA signal is received.
 • Can the microprocessor be interrupted
again before the completion of the ISR?
• As soon as the 1st interrupt arrives,
The 8085 Non- all maskable interrupts are
disabled.
Vectored Interrupt • They will only be enabled after the
Process (INTR) - execution of the EI instruction.
Issues in
Implementing INTR Therefore, the answer is: “only if we
Interrupts allow it to”.
If the EI instruction is placed early in the
ISR, other interrupt may occur before
the ISR is done.
 The 8085 Non-Vectored Interrupt Process
(INTR) - Multiple Interrupts & Priorities

• How do we allow multiple devices to interrupt using the INTR line?

• The microprocessor can only respond to one signal on INTR at a time.
• Therefore, we must allow the signal from only one of the devices to reach the
microprocessor.
• We must assign some priority to the different devices and allow their signals to reach
the microprocessor according to the priority.
 The 8085 Non-Vectored Interrupt Process
(INTR) - The Priority Encoder

• The solution is to use a circuit called the priority encoder (74LS148 / 74LS138).
• This circuit has 8 inputs and 3 outputs.
• The inputs are assigned increasing priorities according to the increasing index of the
input.
• Input 7 has highest priority and input 0 has the lowest.
• The 3 outputs carry the index of the highest priority active input.
 The 8085 Non-Vectored Interrupt Process
(INTR) - Multiple Interrupts & Priorities

• Note that the opcodes for the different RST instructions follow a set pattern.
• Bit D5, D4 and D3 of the opcodes change in a binary sequence from RST 7 down to RST 0.
• The other bits are always 1.
• This allows the code generated by the 74366 to be used directly to choose the appropriate RST
instruction.

• The one draw back to this scheme is that the only way to change the priority of the devices connected to
the 74366 is to reconnect the hardware.
The 8085 Non-
Vectored
Interrupt
Process (INTR) -
The Priority
Encoder
The 8085 Maskable/Vectored Interrupts
• The 8085 has 3 Masked/Vectored
interrupt inputs.
• RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically
vectored according to
the following table:
• The vectors for these
interrupt fall in between
the vectors for the RST
instructions. That’s why
they have names like RST
5.5 (RST 5 and a half).
 Masking RST 5.5, RST 6.5 and RST 7.5

• These three interrupts are masked at two levels:

• Through the Interrupt Enable flip flop and
• The EI/DI instructions.
• The Interrupt Enable flip flop controls the whole maskable interrupt process.
• Through individual mask flip flops that control the availability of the individual interrupts.
These flip flops control the interrupts individually.
Maskable Interrupts and vector locations
RST7.5 Memory
RST 7.5

M 7.5

RST 6.5

M 6.5

RST 5.5

M 5.5

INTR

Interrupt
Enable
Flip Flop
The 8085 Vectored Maskable Interrupt
Process (RST)
1. The interrupt process should be enabled using the EI instruction.
2. The 8085 checks for an interrupt during the execution of every instruction.
3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor
will complete the executing instruction, and reset the interrupt flip flop.
4. The microprocessor then executes a call instruction that sends the execution to the appropriate
location in the interrupt vector table.
5. When the microprocessor executes the call instruction, it saves the address of the next instruction
on the stack.
6. The microprocessor jumps to the specific service routine.
7. The service routine must include the instruction EI to re-enable the interrupt process.
8. At the end of the service routine, the RET instruction returns the execution to where the program
was interrupted.
 Since there is no requirement to supply ISR addresses with direct
interrupts ( TRAP, RST 5.5, RST 6.5 & RST 7.5 ) then there is no
requirement for the 8085A to execute INTA machine cycles in
response to such interrupts.
However to provide the CPU sufficient time to process direct interrupt
Machine - six T-state bus idle machine cycle is introduced, following
recognition of the direct interrupt.

Cycles with During the bus idle machine cycle, no control signal is asserted nor is
the program counter incremented. Ready line control is ignored
Direct during the bus idle cycle.

Interrupts Following with the bus idle cycle which is two memory write cycles
are executed to save the current contents of the program counter on
(Vectored) the stack.

The program counter is then overwritten with the pre-programmed

address for the particular interrupt source.

49
Machine Cycles with Direct Interrupts (Vectored)

Normal operation cycles

* No INTA machine cycle – Direct Interrupt

Since there is no requirement to supply ISR addresses with direct
interrupts ( TRAP, RST 5.5, RST 6.5 & RST 7.5 ) then there is no
requirement for the 8085A to execute INTA machine cycles in response
to such interrupts. 50
Machine Cycles with Direct Interrupts (Vectored)

* No INTA machine cycle – Direct Interrupt

However to provide the CPU sufficient time to process direct interrupt -
six T-state bus idle machine cycle is introduced, following recognition of
the direct interrupt.
51
Machine Cycles with Direct Interrupts
(Vectored)

* No INTA machine cycle – Direct Interrupt

During the bus idle machine cycle, no control signal is asserted nor is the
program counter incremented. Ready line control is ignored during the
bus idle cycle.
52
Machine Cycles with Direct Interrupts
(Vectored)

* No INTA machine cycle – Direct Interrupt

Following with the bus idle cycle which is two memory write cycles are
executed to save the current contents of the program counter on the
stack.
53
Machine Cycles with Direct Interrupts
(Vectored)

* No INTA machine cycle – Direct Interrupt

The program counter is then overwritten with the pre-programmed
address for the particular interrupt source.
54
 • The Interrupt Enable flip flop is
manipulated using the EI/DI
instructions.
• The individual masks for RST 5.5, RST
6.5 and RST 7.5 are manipulated using
Manipulating the SIM instruction.
• This instruction takes the bit
the Masks pattern in the Accumulator and
applies it to the interrupt mask
enabling and disabling the specific
interrupts.
How SIM Interprets the Accumulator
7 6 5 4 3 2 1 0

M6.5
SDO

M5.5
M7.5
SDE

MSE
XXX

R7.5
Serial Data Out RST5.5 Mask

RST7.5 }
RST6.5 Mask 0 - Available
1 - Masked

Mask
Mask Set Enable
Enable Serial Data
0 - Ignore bits 0-2
0 - Ignore bit 7
1 - Set the masks according
1 - Send bit 7 to SOD pin
to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

 • Bit 0 is the mask for RST 5.5
• Bit 1 is the mask for RST 6.5
• Bit 2 is the mask for RST 7.5.
• If the mask bit is 0, the interrupt is available.
• If the mask bit is 1, the interrupt is masked.
• Bit 3 (Mask Set Enable - MSE) is an enable for setting
the mask.
• If it is set to 0 the mask is ignored and the
SIM and the old settings remain.
• If it is set to 1, the new setting are applied.

Interrupt Mask • The SIM instruction is used for multiple

purposes and not only for setting interrupt
masks.
• It is also used to control functionality
such as Serial Data Transmission.
• Therefore, bit 3 is necessary to tell the
microprocessor whether or not the
interrupt masks should be modified
 • The RST 7.5 interrupt is the only 8085 interrupt
that has memory.
• If a signal on RST7.5 arrives while it is
masked, a flip flop will remember the signal.
• When RST7.5 is unmasked, the
microprocessor will be interrupted even if
the device has removed the interrupt signal.
SIM and the • This flip flop will be automatically reset when
the microprocessor responds to an RST 7.5
Interrupt Mask interrupt.

• Bit 4 of the accumulator in the SIM instruction

allows explicitly resetting the RST 7.5 memory
even if the microprocessor did not respond to it.
• Bit 5 is not used by the SIM instruction
 Triggering Levels
• RST 7.5 is positive edge sensitive.
• When a positive edge appears on the RST7.5
line, a logic 1 is stored in the flip-flop as a
“pending” interrupt.
• Since the value has been stored in the flip
flop, the line does not have to be high when
the microprocessor checks for the interrupt
to be recognized.
• The line must go to zero and back to one
before a new interrupt is recognized.
• RST 6.5 and RST 5.5 are level sensitive.
• The interrupting signal must remain present
until the microprocessor checks for
interrupts.
Determining the
Current Mask
Settings
• RIM instruction: Read Interrupt Mask
• Load the accumulator with an 8-bit pattern
showing the status of each interrupt pin
and mask.
RIM sets the
Accumulator’s
different bits
 The RIM Instruction and the Masks

They return the contents of the three mask flip flops.

Bits 0-2 show the current setting of the mask
They can be used by a program to read the mask settings in
for each of RST 7.5, RST 6.5 and RST 5.5 order to modify only the right mask.

It returns the contents of the Interrupt Enable Flip Flop.

Bit 3 shows whether the maskable interrupt
It can be used by a program to determine whether or not
process is enabled or not. interrupts are enabled.
 The RIM Instruction and the Masks

Bits 4 and 5 return the current value of the RST5.5 and RST6.5
Bits 4-6 show whether or not there are pending pins.
interrupts on RST 7.5, RST 6.5, and RST 5.5 Bit 6 returns the current value of the RST7.5 memory flip flop.

The RIM instruction reads the value of the SID pin on the
Bit 7 is used for Serial Data Input. microprocessor and returns it in this bit.
 • Since the 8085 has five interrupt lines,
interrupts may occur during an ISR and remain
Pending pending.
• Using the RIM instruction, it is possible to
Interrupts can read the status of the interrupt lines
and find if there are any pending interrupts.
 • TRAP is the only non-maskable interrupt.
• It does not need to be enabled
because it cannot be disabled.
• It has the highest priority amongst
interrupts.
• It is edge and level sensitive.
• It needs to be high and stay high to be
TRAP recognized.
• Once it is recognized, it won’t be
recognized again until it goes low, then
high again.

• TRAP is usually used for power failure and

emergency shutoff.
The 8085
Interrupts
Summary
 Write a program to count continuously in binary with one second delay between each
Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with
some appropriate delay between flash

Main program
Service routine
LXI SP, XX99H XX70: SERV: PUSH B
EI PUSH PSW
MVI A, 00H MVI B, 0AH
MVI A, 00H
NXTCNT: OUT PORT1
FLASH: OUT PORT1
MVI C, 01H MVI C, 01H
CALL DELAY CALL DELAY
INR A CMA
JMP NXTCNT DCR B
JNZ FLASH
POP PSW
POP B
Interrupt instr: EF EI
At 0028H JMP xx70H RET
Using SIM instruction to Modify the Interrupt Mask
Example 1 : Set the interrupt masks so that RST 7.5 and RST 5.5
is enable and disable RST6.5

Determine the contents of the Accumulator

Enable RST 5.5 bit 0 = 0

Disable RST 6.5 bit 1 = 1

M7.5
M6.5
M5.5
SDO

MSE
R7.5
SDE
XXX
Enable RST 7.5 bit 2 = 0
Allow setting the masks bit 3 = 1
Don’t reset the flip flop bit 4 = 0 0 0 0 0 1 0 1 0
Bit 5 is not used bit 5 = 0
Don’t use serial data bit 6 = 0 Contents of accumulator are: 0AH
Serial data is ignored bit 7 = 0

MVI A, 0A H
SIM ;Set Interrupt Mask
EI ;Enable Interrupt
Using SIM instruction to Modify the Interrupt Mask
Example 2 : Reset RST 7.5 interrupt from example 1

Determine the contents of the Accumulator

Enable RST 5.5 bit 0 = 0

Disable RST 6.5 bit 1 = 1

M7.5
M6.5
M5.5
SDO

MSE
R7.5
SDE
XXX
Enable RST 7.5 bit 2 = 0
Allow setting the masks bit 3 = 1
Reset the flip flop bit 4 = 1 0 0 0 1 1 0 1 0
Bit 5 is not used bit 5 = 0
Don’t used serial data bit 6 = 0 Contents of accumulator are: 1AH
Serial data is ignored bit 7 = 0

MVI A, 1A H
SIM ;Set Interrupt Mask
EI ;Enable Interrupt