Asic Library Design
Asic Library Design
Figure 3.1 A model for CMOS logic delay. (a) A CMOS inverter with load capacitance. (b) Input and output waveforms
showing the definition of falling propagation delay tPDF. (c) The switch model of the inverter showing parasitic
resistances and capacitances.
Effect of Load Capacitance on Inverter
Figure 3.3
Performance
Simulation of an inverter
driving a variable number of
gates on its output
Parasitic Capacitances of a CMOS
Transistor Figure 3.4 Transistor parasitic
capacitance. (a) An N-
channel MOS transistor
with gate length L and
width W. (b) The
components of the gate
capacitance. (c)
Approximating
capacitances with planar
components. (d) The
components of the diffusion
capacitance. (e)-(h) The
dimensions of the gate,
overlap, and sidewall
capacitances.
CMOS Inverter: Steady State Response
VDD VDD
RPon
VOH = VDD
Vout
Vout VOL = 0
RNon VM = f(RNon,RPon)
RNon 1/WN
Vin = V DD Vin = 0
RPon 1/WP
5 NMOS sat
PMOS lin
4
NMOS sat
3
PMOS sat
2
NMOS lin
PMOS sat NMOS lin
1
PMOS off
1 2 3 4 5 Vin
The Ideal Gate
Vout
Ri =
Ro = 0
g=
Vin
Vm = Vdd/2
Figures from material provided with Digital Integrated Circuits, A Design
Perspective, by Jan Rabaey, Prentice Hall, 1996
Balanced CMOS Inverter
Assume that due to differences in mp and mn, for a minimum
sized transistor, Rp = 2Rn
For a balanced inverter we want RP = RN, so in this case, WP
must be 2WN
VDD
WP/LP = 2/1
Vin Vout
CL
WN/LN = 2/1
Logical Effort
Figure 3.8 Logical effort. (a) The input capacitance looking into the input capacitance of a minimum size inverter. (b) Sizing a
logic cell’s transistors to have the same delay as a minimum size inverter. (c) The logical effort of a cell is C in/Cinv.
Logical Effort Of a Complex Gate
Figure 3.10 An AOI221 cell with logical effort vector g=(8/3, 8/3, 7/3).
The Basic Trade-off
to other gates (fanout)