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Asic Library Design

The document discusses ASIC library design and optimization of standard cell performance. It covers: 1) ASIC design uses predefined library cells optimized for speed and area without knowledge of the specific application. 2) The load each cell will drive, such as wire load and fanout, affects its performance. 3) Optimizing transistor sizing and logical effort allows library cells to provide consistent speed across different loads.

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248 views12 pages

Asic Library Design

The document discusses ASIC library design and optimization of standard cell performance. It covers: 1) ASIC design uses predefined library cells optimized for speed and area without knowledge of the specific application. 2) The load each cell will drive, such as wire load and fanout, affects its performance. 3) Optimizing transistor sizing and logical effort allows library cells to provide consistent speed across different loads.

Uploaded by

S RAVI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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ASIC Library Design

ASIC Library Design


• ASIC design is usually performed using a predefined
and precharacterized library of cells
• In designing this library, the original designer had to
optimize speed and area without knowing the actual
application that the cells will be used for - i.e., how
large a load they will be driving
– wire load
– fanout load
• Being aware of the source and effect of these trade-
offs will make it easier to understand how to optimally
design using the library cells
Model of CMOS Inverter with Parasitic
Resistances and Capacitances

Figure 3.1 A model for CMOS logic delay. (a) A CMOS inverter with load capacitance. (b) Input and output waveforms
showing the definition of falling propagation delay tPDF. (c) The switch model of the inverter showing parasitic
resistances and capacitances.
Effect of Load Capacitance on Inverter
Figure 3.3
Performance
Simulation of an inverter
driving a variable number of
gates on its output
Parasitic Capacitances of a CMOS
Transistor Figure 3.4 Transistor parasitic
capacitance. (a) An N-
channel MOS transistor
with gate length L and
width W. (b) The
components of the gate
capacitance. (c)
Approximating
capacitances with planar
components. (d) The
components of the diffusion
capacitance. (e)-(h) The
dimensions of the gate,
overlap, and sidewall
capacitances.
CMOS Inverter: Steady State Response
VDD VDD

RPon
VOH = VDD
Vout
Vout VOL = 0

RNon VM = f(RNon,RPon)

RNon  1/WN
Vin = V DD Vin = 0
RPon  1/WP

Figures from material provided with Digital Integrated Circuits, A Design


Perspective, by Jan Rabaey, Prentice Hall, 1996
CMOS Inverter VTC

Vou t NMOS off


PMOS lin

5 NMOS sat
PMOS lin
4

NMOS sat
3

PMOS sat
2

NMOS lin
PMOS sat NMOS lin
1

PMOS off

1 2 3 4 5 Vin
The Ideal Gate

Vout

Ri = 

Ro = 0
g= 

Vin

Vm = Vdd/2
Figures from material provided with Digital Integrated Circuits, A Design
Perspective, by Jan Rabaey, Prentice Hall, 1996
Balanced CMOS Inverter
Assume that due to differences in mp and mn, for a minimum
sized transistor, Rp = 2Rn
For a balanced inverter we want RP = RN, so in this case, WP
must be 2WN
VDD

WP/LP = 2/1

Vin Vout

CL

WN/LN = 2/1
Logical Effort

Figure 3.8 Logical effort. (a) The input capacitance looking into the input capacitance of a minimum size inverter. (b) Sizing a
logic cell’s transistors to have the same delay as a minimum size inverter. (c) The logical effort of a cell is C in/Cinv.
Logical Effort Of a Complex Gate

Figure 3.10 An AOI221 cell with logical effort vector g=(8/3, 8/3, 7/3).
The Basic Trade-off
to other gates (fanout)

to other gates (fanout)

Which is faster? buffer


to other gates (fanout)

to other gates (fanout)

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