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VHDL

VHDL is a hardware description language used to model digital circuits. It has constructs like entities to define input/output ports, architectures to describe a design's functionality, and configurations to associate architectures with entities. Common logic gates like AND, OR, and NOT can be modeled using VHDL signal assignments and if/else statements within processes. The document provides examples of VHDL code to describe a multiplexer circuit.

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Marlofel Paradero
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93 views25 pages

VHDL

VHDL is a hardware description language used to model digital circuits. It has constructs like entities to define input/output ports, architectures to describe a design's functionality, and configurations to associate architectures with entities. Common logic gates like AND, OR, and NOT can be modeled using VHDL signal assignments and if/else statements within processes. The document provides examples of VHDL code to describe a multiplexer circuit.

Uploaded by

Marlofel Paradero
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VHDL

Very High Speed Integrated Circuits


Hardware Description Language
VHDL VS VERILOG
• VHDL: Very High Speed Integrated Circuits
Hardware Description Language
– Developed by DOD from 1983
– IEEE Standard 1076-1987/1993/200x
– Based on the ADA language
• Verilog
– IEEE Standard 1364-1995/2001/2005
– Based on the C language
REVIEW OF BASIC LOGIC GATES

• NOT GATE, AND & OR GATES


NOT GATE
VHDL
A = NOT B
AND GATE

VHDL
C
C = A AND B

NOTE:
IF B = 0 , C = 0
IF B = 1 , C = A

THEREFORE:
AND GATE IS COMMONLY
USED AS A CONTROLLED
BUFFER
OR GATE

VHDL C

C = A OR B C
TERMINOLOGY
HDL- HARDWARE DESCRIPTION LANGUAGE
- IS A SOFTWARE PROGRAMMING LANGUAGE THAT IS USED TO MODEL A
PIECE OF HARDWARE
BEHAVIOR MODELLING
- A COMPONENT DESCRIBED ITS INPUT/OUTPUT RESPONSE.
STRUCTURAL MODELLING
- A COMPONENT IS DESCRIBED BY INTERCONNECTING LOWER LEVEL
COMPONENTS/ PRIMITIVES.
REGISTER TRANSFER LEVEL (RTL)
A TYPE OF BEHAVIORAL MODELLING FOR THE PURPOSE OF SYNTHESIS.
SYNTHESIS
-TRANSLATING HDL TO A CIRCUIT AND THEN OPTIMIZING REPRESENTED
CIRCUIT.
PROCESS
- BASIC UNIT OF EXECUTION IN VHDL
4 VHDL DESIGN UNITS
• ENTITY
- USE TO DEFINE EXTERNAL VIEW OF A MODEL
• ARCHITECTURE
- USE TO DEFINE FUNCTION OF A MODEL
• CONFIGURATION
- USED TO ASSOCIATE ARCHITECTURE WITH AN
ENTITY.
• PACKAGE
- COLLECTION OF INFORMATION THAT CAN BE
REFERENCED BY VHDL MODELS.
Signal Assignment Operator
To assign a value to a signal data object in VHDL,
we use the
signal assignment operator

<=
Example:

y <= ‘1’; -- signal y is assigned the value ONE


VHDL Statement Terminator
Each VHDL Statements is terminated using a
semicolon

;
VHDL Comment Operator
To include a comment in VHDL, use the
comment operator

-- This is a comment
-- This is an example of a comment
y <= 0; -- can occur at any point
Input-Output specification of circuit

 Example: my_ckt
 Inputs: A, B, C
 Outputs: X, Y
A  VHDL description:
X
B my_ckt entity my_ckt is
Y port (
S A: in bit;
B: in bit;
S: in bit;
X: out bit;
Y: out bit);
end my_ckt ;

Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated) 17


VHDL entity
• entity my_ckt is Datatypes:
 Name of the circuit
 In-built
port (  User-defined
 User-defined
A: in bit;  Filename same as circuit name
B: in bit; A Example.
recommended
  Circuit name: my_ckt
Example: X
S: in bit;  Circuit
Filename:
name:
my_ckt.vhd
my_ckt
B my_ckt
X: out bit;  Filename: my_ckt.vhd Y
Y: out bit S
); Direction of port
end my_ckt; 3 main types:
 in: Input
Port names or  out: Output
Note the absence of semicolon “;” at
Signal names the end ofthe
inout: Bidirectional
last signal and the
presence at the end of the closing
bracket
Fall 08, Oct 29 ELEC2200-002 Lecture 7 (updated) 18
VHDL Design Organization

• Entity
the “symbol” (input/output ports)
• Architecture
one of the several possible implementation of the
design
• Configuration
binding between the symbol and one of the many
possible implementation.
Can be used to express hierarchy.

19
VHDL Design Organization
• Libraries
logical units that are mapped to physical directories. The units of a library are called packages.
• Packages
repositories for type definitions, procedures, and functions
• Libraries and packages can be system defined or user defined

package
package
specification of the
declaration
package contents

package body code blocks

20
Design Units
• Primary design units (not dependent on other design units)
– Entity
– Configuration
– Package Declaration

• Secondary design units


– Package body
– Architecture

• Design units are arranged in files

• Now you know the layout of a VHDL program!


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Entity

entity mux is
MUX port (
a: in std_logic;
A b: in std_logic;
B F s: in std_logic;
S f: out std_logic
)
end mux;

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Architecture

architecture first_rtl of mux is


begin
mux_p: process (a,b,s)
begin
f <= (a and s) or (b and not s);
end process mux_p;
end first_rtl;

23
Architecture #2
architecture rtl of mux is
begin
mux_p: process (a,b,s)
begin
if (s=‘1’) then
f <= a;
else
f <= b;
end if;
end process mux_p;
end rtl;

24
Configuration

configuration mux_c of mux is


for rtl
end for;
end mux_c;

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