THE COMPUTER SYSTEM

Computer function and

Interconnection
o Computer functions
o Interconnection Structures
o Bus Interconnection
Structure & Function
• Structure is the way in which components
relate to each other
• Function is the operation of individual
components as part of the structure
Function
• All computer functions are:
—Data processing
—Data storage
—Data movement
—Control
Functional View
Operations (a) Data movement
Operations (b) Storage
Operation (c) Processing from/to storage
Operation (d)
Processing from storage to I/O
 Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
Hardwired Program
• For every instruction there is a small set of basic
logic components are used
• These component can be combined in various ways
to store binary data and to perform arithmetic and
logical operations on data
• For each computation , a confirmation of logic
component is design.
• This is as ‘process of connecting the various
components in desire configuration as form of
programming ‘
• This resulting program is in form of hard ware so
known as hardwired program
• Program is actually sequence of steps and
for each step some arithmetic and logical
operation is performed on some data
• we need to provide the general purpose
hardware program that can accept a code
and generate control signal
• So instead of rewriting hardware for each
new program, we need to provide a new
sequence of codes
• Each codes nothing but instruction and
part of hardware interpret each instruction
and generates control signal
• This new method is called as software
 Sequence of
Data arithmetic and Result
logic functions

Programming in Hardware

Instruction Instruction
code interpreter
Control signal

General purpose
Data arithmetic and Result
logic functions

Hardware and Software Approaches

What is a program?
• A sequence of steps
• For each step, an arithmetic or logical
operation is done
• For each operation, a different set of
control signals is needed
Function of Control Unit
• For each operation a unique code is
provided
—e.g. ADD, MOVE
• A hardware segment accepts the code and
issues the control signals
CPU Components
• The Control Unit and the Arithmetic and
Logic Unit constitute the Central
Processing Unit
• Data and instructions need to get into the
system and results out
—Input/output
• Temporary storage of code and results is
needed
—Main memory
Computer Components:
Top Level View
Instruction Format
0 34 15

Opcode

Ex.Opcodes
0001 = Load AC from Memory
0010 = Store AC to Memory
0101= Add to AC from Memory
Instruction Cycle
• Two steps:
—Fetch
—Execute
Fetch Cycle
• Program Counter (PC) holds address of
next instruction to fetch
• Processor fetches instruction from
memory location pointed to by PC
• Increment PC
—Unless told otherwise
• Instruction loaded into Instruction
Register (IR)
• Processor interprets instruction and
performs required actions
Execute Cycle
• Processor-memory
—data transfer between CPU and main memory
• Processor I/O
—Data transfer between CPU and I/O module
• Data processing
—Some arithmetic or logical operation on data
• Control
—Alteration of sequence of operations
—e.g. jump
• Combination of above
Example of Program Execution
Instruction Cycle Diagram
Interrupts
• Mechanism by which other modules (e.g.
I/O) may interrupt normal sequence of
processing
• Program
—e.g. overflow, division by zero
• Timer
—Generated by internal processor timer
—Used in pre-emptive multi-tasking
• I/O
—from I/O controller
• Hardware failure
—e.g. memory parity error
Interrupts
Instruction Cycle with interrupt Diagram
Interconnection Structures
• A computer consists of a set of
components (CPU,memory,I/O) that com
municate with each other.
• The collection of paths connecting the
various modules is call the interconnection
structure.
• The design of this structure will depend on
the exchange that must be made between
modules.
 Input/Output for each module

Read Read
Write Write
Memory
N Word
Internal
Data
0 Data
Address .
.
.
Address External
Data N-1 I/O Module Data
Internal
Data
Interrupt
Signal
External
Data

Instructions
Data
Interrupt Signal CPU Control
Signal
Data
Type of transfers
• Memory to CPU
• CPU to Memory
• I/O to CPU
• CPU to I/O
• I/O to or from Memory (DMA)
Bus Interconnection
• A bus is a communication pathway
connecting two or more device.
• A key characteristic of a bus is that it is a
shared transmission medium.
• A bus consists of multiple pathways or
lines.
• Each line is capable of transmitting signal
representing binary digit (1 or 0)
Bus Interconnection
• A sequence of bits can be transmit across
a single line.
• Several lines can be used to transmit bits
simultaneously (in parallel).
• A bus that connects major components
(CPU,Memory,I/O) is called System Bus.
• The most common computer
interconnection structures are based on th
e use of one or more system buses.
Bus Structure
• A system bus consists of 50-100 lines.
• Each line is assigned a particular meaning or
function.
• On any bus the lines can be classified into 3
groups
—Data Bus
—Address Bus
—Control Bus
Data Bus
• Provide a path for moving data between system
modules.
• These lines, collectively, are called the data bus
• The data bus typically consists of 8,16 or 32
separate lines, the numbers of lines being transfe
rred to as the width of the data bus.
• Each line carry only 1 bit at a time, the number
of lines determines how many bits can transferre
d at a time - overall system performance.
The Address Bus
• Used to designate the source or
destination of the data on the data bus
• The width of the address bus determines
the maximum possible memory capacity o
f the system.
The Control Bus

• Used to control the access to and the use

of the data and address lines.
• Typical control lines include
—Memory write
—Memory read
—I/O write
—Bus request
—I/O read
—Clock —Bus grant
—Reset —Interrupt request
—Interrupt ACK
—Transfer ACK
The operation of the bus

If one module wishes to send data

• obtain the use of the bus
• transfer data via the bus
If one module wishes to request data
• obtain the use of the bus
• transfer request to the other module over the
control and address lines, then wait for that
second module to send the data.
 Physical Bus Architecture

• System bus is a number of

parallel electrical conductors.
• The conductors are metal
lines etched in a card or print
ed circuit board.
• The bus extends across all of
the components tat taps into
the bus lines.
buses look like
Multiple-Bus Hierarchies
• More devices attached to bus, propagation
delays affect performance

• Bottleneck as the aggregate data

transfer demand approaches capacity o
f bus.
(e.g graphics & video controller)
Traditional Bus Architecture

• Local bus
—CPU - Cache
• System bus
—Main memory - Cache
• Expansion bus
—I/O Modules - Main memory
Traditional Bus Architecture
High-Performance Architecture

• Local bus
—CPU - Cache/bridge
• System bus
—Cache/bridge - memory
• High-speed bus
—High-speed I/O module - Cache/bridge
• Expansion bus
—Low-speed I/O modules - Expansion interface
High-Performance Architecture
Bus Design

• Type  Method of Arbitration

—Dedicated  Centralized
—Multiplexed

Distributed
• Bus Width  Data Transfer Type
—Address  Read
—Data  Write

• Timing  Read-modify-write

—Synchronous  Read-after-write

—Asynchronous  Block
Type
• Dedicated
permanent assigned bus either to
one function or to a physical subset o
f computer components
• Multiplexed

use in the same bus for multiple

purpose`
Bus Width
• Address
the wider of address bus has an
impact on range of locations that can
be referenced
• Data
the wider of data bus has an
impact on the number of bits transferr
ed at one time
Timing
• Synchronous • Asynchronous

occurrence
occurrence of events of one event follows
on the bus is and depends on the
determined by a cloc previous event.
k (Clock Cycle or Bus
Cycle)
Method of Arbitration
• Centralized • Distributed
bus access control
controller (Arbiter), ha
rdware device,is resp logic in each module a
onsible for allocating ct together to share b
time on the bus (daisy us
chain)
Data Transfer Type
• Read Multiplexed
bus is used to specifying address and
then for transferring data after a wait
while data is being fetched
• Read Dedicated
address is put on bus and
remain there while data are put on the da
ta bus
Data Transfer Type
• Write Multiplexed
bus is used to specifying address
and then transferring data (same as read
operation)
• Write Dedicated
data put on data bus as soon as
the address has stabilized
Data Transfer Type
• Read-modify-write
address is broadcast once at
beginning a simply read is followed immed
iately by a write to the same address
• Read-after-write
a write followed
immediately by a read from the same ad
dress,performed for checking purposes
Data Transfer Type
• Block
one address cycle is followed by n data
cycles.

The first data item is transferred to or

from the specified address; remainder da
ta items are transferred to or from subse
quent addresses
Data Transfer Type
Samples of Bus
• ISA (Industry Standard Architecture)
• MCA (Micro Channel Architecture)
• EISA (Extended ISA)
• VL Bus (VESA Local Bus)
• PCI Bus (Peripheral Connection Interface)
Industry Standard Architecture

• ISA is a standard bus (computer

interconnection) architecture that is assoc
iated with the IBM AT motherboard.
• It allows 16 bits at a time to flow
between the motherboard circuitry and
an expansion slot card and its associate
d device(s).
Industry Standard Architecture
Micro Channel Architecture
• Developed by IBM for its line of PS/2 desktop
computers, MCA is an interface between a compute
r (or multiple computers) and its expansion cards a
nd their associated devices.
• MCA was a distinct break from previous bus
architectures such as ISA.
• The pin connections in MCA are smaller than other
bus interfaces. For this and other reasons, MCA
does not support other bus architectures.
Micro Channel Architecture
(cont.)

• Although MCA offers a number of

improvements over other bus architecture
s, its proprietary, nonstandard aspects did
not encourage other manufacturers to ado
pt it.
• It has influenced other bus designs and it
is still in use in PS/2s and in some minico
mputer systems.
Extended Industry Standard
Architecture
• EISA is a standard bus architecture that
extends the ISA standard to a 32-bit interf
ace. It was developed in part as an open a
lternative to the proprietary Micro Channel
Architecture (MCA) that IBM introduced in
its PS/2 computers.
• EISA data transfer can reach a peak of 33
megabytes per second
VESA[Video Electronics Standards
Association ]Local Bus
• VESA VL bus is a standard interface
between your computer and its expansion sl
ot that provides faster data flow between th
e devices controlled by the expansion cards
and your computer's microprocessor.
• A "local bus" is a physical path on which
data flows at almost the speed of the
microprocessor, increasing total system perf
ormance.
VESA Local Bus (cont.)

• VESA Local Bus is particularly effective

in systems with advanced video cards a
nd supports 32-bit data flow at 50 MHz
• A VESA Local Bus is implemented by
adding a supplemental slot and card th
at aligns with and augments an ISA ex
pansion card. (ISA is the most common
expansion slot in today's computers.)
Peripheral Component Interconnect

• PCI is an interconnection system between

a microprocessor and attached devices in
which expansion slot are spaced closely fo
r high speed operation.
• Using PCI, a computer can support both
new PCI cards while continuing to support
ISA expansion cards, currently the most c
ommon kind of expansion card.
Peripheral Component Interconnect
(cont.)
• Designed by Intel, the original PCI was similar to the
VESA Local Bus.
• PCI2.0 is no longer a local bus and is designed to be
independent of microprocessor design.
• PCI is designed to be synchronized with the clock
speed of the microprocessor, in the range of 33 to
66 MHz.
• Standard : Up to 64 data-lines at 66 MHz. Raw
transfer rate of 528 MBps or 4.224 Gbps.
Peripheral Component Interconnect
(cont.)
• PCI is now installed on most new desktop
computers, not only those based on Intel's
Pentium processor but also those based o
n the PowerPC.
• PCI transmits 32 bits at a time in a 124-
pin connection (the extra pins are for
power supply and grounding) and 64 bits i
n a 188-pin connection in an expanded im
plementation.
Peripheral Component Interconnect
(cont.)
• PCI uses all active paths to transmit both
address and data signals, sending the add
ress on one clock cycle and data on the ne
xt.
• PCI deliver better system performance for
high-speed I/O subsystems
e.g. graphic display adapters, network
interface controllers, disk controllers
PCI Bus Structure
 PCI

A Desktop System

A Server System
Universal Serial Bus
• Standard bus which is invented by a group of
companies : Compaq, DEC, IBM, Intel, Microsoft,
NEC, Northern Telecom, etc.
• Not change switch, jumper on board or other
devices
• Can use the same cable
• Device that use USB can use power supply from
PC.
• Up to 127 devices connected off single port
• Support real-time system
• Hot Plug-in
• Low cost
Multi-System Buses